DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 11-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 20190288702 A1).
In regard to Claim 1:
Zhang discloses, in Figure 1A, a programmable gain amplifier comprising:
an amplifier (101) having an inverting input (negative terminal of 101) and a noninverting input (positive terminal of 101) and an amplifier output (output of 101);
a set of resistors (R1-R11) coupled between a first node (R_EQ node) and a second node (node between R1 and R2), wherein the first node is coupled to the amplifier output (output of 101);
a first switch (S1) coupled between the second node (node 110) and ground (ground to the right of node 110);
a first current path (path from node between R1 and R2 through S2) between a third node (node between R1 and R2) in the set of resistors (R1-R11) and a tap point (node 1), the first current path including a second switch (S2);
a second current path (path from node, between R2 and R3, through S3) between a fourth node (between R2 and R3) in the set of resistors (R1-R11) and the tap point (node 1), the second current path including a third switch (S3); and
a feedback path (path through nodes 128-1) coupled between the tap point of the set of resistors and the inverting input (negative terminal of 101) of the amplifier (101);
wherein the set of resistors (R1-R11) includes a first resistors (R3) coupled between the third node (node between R1 and R2) and the fourth node (between R2 and R3).
In regard to Claim 11:
Zhang discloses a circuit comprising a set of resistors (R1-R11) coupled in series having a first node (R_EQ) coupled to an amplifier output (output of 101) and a second node (node between R1 and R2) coupled to ground; a feedback path (path through nodes 128-1) coupling a tap point (node 1) of the set of resistors (R1-R11) to an amplifier input (input of 101); and a first switch (S1), a second switch (S2), and a third switch (S3), wherein; the first switch (S1) is coupled between the second node (S2) of the set of resistors (R1-R11) and the ground, a first current path (path from node between R1 and R2 through S2) is coupled between a third node (node between R1 and R2) of the set of resistors (R1-R11) and the tap point (node 1), the first current path (path from node between R1 and R2 through S2) including the second switch (S2), wherein the first current path )path from node between R1 and R2 through S2) is parallel to a first portion of the set of resistors (R1-R11), a second current path (path from node, between R2 and R3, through S3) is coupled between a fourth node in the set of resistors (R1-R11) and the tap point (node 1), the second current path (path from node, between R2 and R3, through S3) is parallel to a second portion of the set of resistors (R1-R11), and the set of resistors (R1-R11) includes a first resistor (R3) coupled between the third node (node between R1 and R2) and the fourth node (between R2 and R3).
In regard to Claim 12:
Zhang discloses a fourth switch (S4) implemented in a third current path (path from node, between R3 and R4, through S4), wherein the third current path couples a fifth node (node between R3 and R4) in the set of resistors (R1-R11) to the tap point (node 1), the third current path (between R3 and R4) being parallel to a third portion of the set of resistors (R1-R11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4, 13, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 20190288702 A1), in view of Pennock (US 6828845 B2).
In regard to Claim 4:
Zhang does not disclose wherein the fourth switch has a larger dimension than a corresponding dimension in either of the second switch or third switch.
In a similar field of endeavor, Pennock discloses wherein the fourth switch (12a or 12b or 12c) has a larger dimension than a corresponding dimension in either of the second switch (14a) or the third switch (14b) (Column 6, lines 55-66).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the switch having a larger dimension than other switches, as taught by Pennock, in combination with the elements taught by Zhang. One would be motivated to do so because Pennock teaches that having one switch larger in dimension than other switches allows for diversion of parasitic currents (Pennock Column 6, lines 59-63).
In regard to Claim 13:
Zhang does not disclose wherein the fourth switch has a larger dimension than a corresponding dimension in either of the second switch or third switch.
In a similar field of endeavor, Pennock discloses wherein the fourth switch (12a or 12b or 12c) has a larger dimension than a corresponding dimension in either of the second switch (14a) or the third switch (14b) (Column 6, lines 55-66).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the switch having a larger dimension than other switches, as taught by Pennock, in combination with the elements taught by Zhang. One would be motivated to do so because Pennock teaches that having one switch larger in dimension than other switches allows for diversion of parasitic currents (Pennock Column 6, lines 59-63).
In regard to Claim 18:
Zhang does not disclose wherein the fourth switch has a larger dimension than a corresponding dimension in either of the second switch or third switch.
In a similar field of endeavor, Pennock discloses wherein the fourth switch (12a or 12b or 12c) has a larger dimension than a corresponding dimension in either of the second switch (14a) or the third switch (14b) (Column 6, lines 55-66).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the switch having a larger dimension than other switches, as taught by Pennock, in combination with the elements taught by Zhang. One would be motivated to do so because Pennock teaches that having one switch larger in dimension than other switches allows for diversion of parasitic currents (Pennock Column 6, lines 59-63).
Claim(s) 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 20190288702 A1), in view of Lu (US 10270407 B2).
In regard to Claim 5:
Zhang does not disclose the fourth switch comprising an NMOS and PMOS in parallel.
In a similar field of endeavor, Lu discloses wherein the fourth switch (Lu; Fig 3; 305-3a ) comprises an NMOS transistor and a PMOS transistor in parallel (Lu; Column 6 lines 30-35).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the fourth switch comprising an NMOS and PMOS in parallel, as taught by Lu, as it provides a switch that is independent of the input-signal (Lu; Column 2 lines 29-30).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 20190288702 A1), in view of Remmers (US 7906976 B2).
In regard to Claim 7:
Zhang does not disclose a fourth switch coupled between the second node and an input voltage node.
In a similar field of endeavor, Remmers discloses wherein a fourth switch (Remmers; Fig 2; S4) coupled between the second node (Remmers; Fig 2; node where S3 and 4 meet) and an input voltage node (Remmers; Fig 2; Vref).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the fourth switch coupled between the second node and an input voltage node, as taught by Remmers, as it provides for a connection for the non-inverting input of the amplifier (Remmers; Column 3 lines 18-20).
In regard to Claim 8:
Zhang does not disclose wherein the amplifier output is coupled to an analog-to-digital converter.
In a similar field of endeavor, Remmers discloses wherein the amplifier output (Remmers; Fig 1; Vout) is coupled to an analog-to-digital converter (Remmers; Fig 1; ADC).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the amplifier output coupled to an analog-to-digital converter, as taught by Remmers, as it provides for an analog signal to be converted to a digital one.
Claim(s) 15, 17, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 20190288702 A1), in view of Hughes (US 20080252378 A1).
In regard to Claim 15:
Zhang discloses an amplifier (101) having a noninverting input, an inverting input, and an amplifier output; a set of resistors (R1-R11) coupled in series between the amplifier output and ground; a plurality of switches (S1-S5).
Zhang does not disclose a control circuit to provide control mechanism for a plurality of switches along with its resulting resistance changes.
In a similar field of endeavor, Hughes discloses, in figure 3b, a control circuit (X31), coupled to the plurality of switches (S1-S4), wherein the control circuit is configured to: control a first switch (S1), of the plurality of switches (S1-S4), to complete a first current path(path from P1 to N31) from a first node (P1) in he set of resistors (R and 2R) to a tap point (N3), wherein the tap point divides a first resistive portion (RA)(RSPAN; Fig 3b) of the set of resistors between the tap point (N3) and ground and a second resistive portion (RB)(2R; Fig 3b) of the set of resistors between the tap point (N3) and the amplifier output (Fig 3b; Out); control a second switch (S2), of the plurality of switches, to complete a second current path (path from P2 to N2) from a second node (P2) in the set of resistors to the tap point (N3); and change a sum of resistance of RA (RSPAN) plus resistance of RB (set of 2R resistors) by turning on the first switch (S1) and turning off the second switch (S2) and by turning off the first switch (S1) and turning on the second switch (S2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the control circuit and all its mechanisms, as taught by Hughes, in combination with the elements taught by Zhang. One would be motivated to do so because Hughes teaches that these plurality of switches and resistors contribute to adjusting the gain (Hughes Page 5, paragraph 56).
In regard to Claim 17:
Zhang does not disclose a control circuit or any of its mechanisms to control a fifth switch and change the sum of resistances.
In a similar field of endeavor, Hughes discloses, in figure 3b, wherein the control circuit (X31) is further configured to control a fifth switch (S3), of the plurality of switches (S1-S4), to complete a third current path (P3 to N33) from a node point in the set of resistors (P3) to the tap point (N3), wherein the third current path (P3 to N33) bypasses the first current path (P1 to N31) and the second current path (P2 to N32); and change the sum of resistance of RA (RSPAN) plus resistance of RB (set of 2R resistors) by selecting among the first switch (S1), the second switch (S2), and the fifth switch (S3).
It would have been obvious to one of ordinary skill in the art, before the effective fling date, to utilize the fifth switch, along with a third current path, to allow for changing of the sum of resistance values, as taught by Hughes, in combination with the elements taught by Zhang. One would be motivated to do so because Hughes teaches that these plurality of switches and resistors contribute to adjusting the gain (Hughes Page 5, paragraph 56)
In regard to Claim 19:
Zhang does not disclose a third current path that comprises an additional set of resistors.
In a similar field of endeavor, Hughes discloses, in figure 3b, wherein the third current path (P3 to N33) comprises an additional set of resistors (resistor R between node N33 and N3, 2R, and RSPAN).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the third current path comprising an additional set of resistors, as taught by Hughes, in combination with the elements taught by Zhang. One would be motivated to do so because Hughes teaches that RSPAN contributes to the adjusting of the gain (Hughes Page 3, paragraph 31).
Allowable Subject Matter
Claim 3, objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 is objected under the following: a fifth switch and sixth switch coupled between the tap point and a sixth and seventh node in the set of resistors respectively; the set of resistors including the first resistor coupled between the sixth and seventh node respectively; the third current path coupled to the tap point via the fifth switch; and the first current path and second current path coupled to the tap point via the sixth switch.
Claim 6 is objected under the following: the second switch comprising an N channel metal oxide semiconductor (NMOS) transistor and a P channel metal oxide semiconductor (PMOS), wherein a drain of the PMOS transistor is coupled to a source of the NMOS transistor, further wherein a body terminal of the PMOS transistor is coupled to the drain of the PMOS transistor through a second PMOS transistor.
Claim 9 is objected under the following: a third current path coupled between the first node and the second node of the set of resistors, the third current path including a fourth switch and another set of resistors coupled in parallel to the set of resistors.
Claim 14 is objected under the following: a third current path coupling the first node of the set of resistors to the second node of the set of resistors, the third current path including a fourth switch and an additional set of resistors in parallel to the set of resistors; a fifth switch coupling a first terminal of a second resistor in the additional set of resistors to the tap point; and a sixth switch coupling a second terminal of the second resistor in the additional set of resistors to the tap point.
Claim 16 is objected under the following: wherein the amplifier is coupled to a first power supply at its noninverting input, and wherein the set of resistors is further coupled to a second power supply, wherein the set of resistors is coupled to ground by a third switch of the plurality of switches and is coupled to the second power supply by a fourth switch of the plurality of switches, further wherein the control circuit Is configured to control the third switch and the fourth switch to provide either inverting or noninverting gain.
Claim 20 is objected under the following: wherein the control circuit is further configured to direct leakage current from the fifth switch, during a time in which the fifth switch is turned off, to ground, including isolating the leakage current from the tap point.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMAAN JAWAD KHAN whose telephone number is (571)270-7266. The examiner can normally be reached M-Th 9-4.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at (571)-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.J.K./Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
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