DETAILED ACTION
This communication is responsive to the application, filed March 5, 2026. Claims 1-20 are pending in this application.
Examined under the first inventor to file provisions of the AIA
The present application was filed on April 29, 2024, which is on or after March 16, 2013, and thus is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 11,971,789 B2 in view of Grosz et al. (US 2020/0004459 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of present application are obvious under the claims of issued patent in view of Grosz. The issued US patent and the instant application are claiming common subject matter. The one of ordinary skill in the art would recognize that they are obvious variants in view of Grosz.
Claims 1-10 are compared to claims 1, 5, and 6 of US patent US 11,971,789 B2 in view of Grosz in the following table:
Instant Application
US Patent No : US 11,971,789 B2
1. A method comprising:
detecting a crash of a storage device with a connection to a host;
suspending, based on detecting the crash of the storage device, processing commands, from the host through the connection;
recovering from the crash of the storage device, wherein recovering from the crash of the storage device comprises:
initiating a first restart operation of a processor of the storage device; and
resuming, based on reloading the portion of the firmware for the processor of the storage device, processing commands from the host through the connection.
preventing the host from detecting a timeout condition based on the crash of the storage device; and
1. A method of operating a storage device comprising:
detecting a crash of the storage device;
suspending, based on detecting the crash, processing commands, from the host through the connection;
recovering from the crash of the storage device, wherein recovering from the crash of the storage device includes:
masking an event of a first type;
initiating a first reset operation of the processor of the storage device;
resuming, based on recovering from the crash, processing commands from the host through the connection, including executing the masked event of a first type.
‘789 discloses detecting a crash of the storage device, but fails to disclose preventing host from detecting timeout condition. Grosz discloses [0009-0011] preventing the host from detecting a timeout condition.
2. The method of claim 1, wherein recovering from the crash of the storage device further comprises: initiating a second restart operation of the processor of the storage device.
1. initiating a second reset operation of the processor of the storage device;
3. The method of claim 2, wherein recovering from the crash of the storage device further comprises: transferring, by the processor of the storage device, data from a first medium of the storage device to a second medium of the storage device.
1. transferring, by the processor of the storage device, data from a first medium of the storage device to a second medium of the storage device; and
4. The method of claim 1, wherein recovering from the crash of the storage device further comprises: masking an event of a first type.
1. recovering from the crash of the storage device, wherein recovering from the crash of the storage device includes:
masking an event of a first type;
5. The method of claim 4, wherein resuming processing commands from the host through the connection, further comprises: executing the masked event of a first type.
1. resuming, based on recovering from the crash, processing commands from the host through the connection, including executing the masked event of a first type.
6. The method of claim 4, wherein recovering from the crash of the storage device further includes processing an event of a second type at a storage interface.
1. recovering from the crash of the storage device, wherein recovering from the crash of the storage device includes: initiating a second reset operation of the processor of the storage device; and
7. The method of claim 6, wherein the event of the second type is one of a port-level reset, a function-level reset, a control transaction, or a memory transaction.
1. recovering from the crash of the storage device, wherein recovering from the crash of the storage device includes: initiating a second reset operation of the processor of the storage device; and
(It is clear that the reset operation is a function-level reset of the processor of the storage device)
8. The method of claim 1, wherein suspending further comprises: suspending, based on detecting the crash, processing commands, via the processor of the storage device, from the host through the connection.
1. suspending, based on detecting the crash, processing commands, via a processor of the storage device, from the host through the connection;
9. The method of claim 1, further comprising: receiving a reset operation from the host; and resetting a storage interface based on receiving the reset operation from the host.
5. The method of claim 2, further comprising:
receiving a third reset operation from the host; and resetting a storage interface based on receiving the third reset operation from the host.
10. The method of claim 9, wherein: the reset operation comprises a controller reset; and resetting the storage interface comprises resetting a controller in the storage interface.
6. The method of claim 5, wherein:
the third reset operation comprises a controller reset; and resetting the storage interface comprises resetting a controller in the storage interface.
Claims 11-18 of the instant application recite a storage device claim and are obvious variants of the method claims 1-10, which are compared in the table above. Furthermore, claims 19 and 20 of the instant application recite a computer-readable storage medium claim and are obvious variants of the method claims 1 and 2, which are compared in the table above. Therefore, claims 11-20 of the instant application are also rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 11,971,789 B2 in view of Grosz.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 5, 8-11, 14, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Freeman et al. (US 2017/0255535 A1) in view of Eny (US 8,892,859 B1) and further in view of Grosz et al. (US 2020/0004459 A1).
As per claim 1: A method comprising:
detecting a crash of a storage device with a connection to a host;
suspending, based on detecting the crash of the storage device, processing commands, from the host through the connection;
Freeman discloses [0021] during a period that a storage device encounters an error, normal access to the storage device by the host computer is prevented and normal operations are suspended.
recovering from the crash of the storage device, wherein recovering from the crash of the storage device comprises:
initiating a first restart operation of a processor of the storage device;
resuming, based on the first restart operation of the processor of the storage device, processing commands from the host through the connection.
Freeman discloses [0029] once the self-diagnosis procedure has been completed, the storage device is returned to service and normal access to the storage device by the host computer is allowed. Freeman discloses self-diagnosis procedure, but fails to explicitly disclose recovery from the crash of the storage device. Eny discloses a similar method, which further teaches [Fig. 1; col. 3, lines 38-54] a storage device that includes a CPU and that would benefit from the ability to implement a full or partial reset of CPU and/or integrated peripheral device control parameters of the storage device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Freeman with that of Eny. One would have been motivated to recover from the crash of the storage device because it allows to return to fully operational state [Eny; col. 3, lines 38-54].
preventing the host from detecting a timeout condition based on the crash of the storage device; and
Freeman and Eny disclose performing full or partial reset and resume from a crash of a storage device to fully operational state, but fail to explicitly disclose preventing the host from detecting a timeout condition. Grosz discloses a similar method, which further teaches [0009-0011] when the memory device is about to reach the host timeout interval, the host timeout avoidance module generates a response to the host. The response may include partial data corresponding to the command or an indication that the memory device is still processing the command. In response, the host may reset a host timeout timer and avoid resetting the memory device. The transmission of the response prevents the host from timing out and sending the reset signal. Grosz further discloses [0017] the memory controller is configured to actively detect and recover from crash conditions of storage of data, while maintaining integrity of the transfer between the host and the storage device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Freeman and Eny with that of Grosz. One would have been motivated to prevent the host from detecting a timeout condition because it avoids inefficiencies and waste of resources on a given command for the memory device [Grosz; 0011].
As per claim 4: The method of claim 1, wherein recovering from the crash of the storage device further comprises: masking an event of a first type.
Eny discloses [Fig. 1; col. 3, lines 38-54] a storage device that includes a CPU and that would benefit from the ability to implement a full or partial reset of CPU (masking an event) and/or integrated peripheral device control parameters of the storage device.
As per claim 5: The method of claim 4, wherein resuming processing commands from the host through the connection, further comprises: executing the masked event of a first type.
Eny discloses [Fig. 1; col. 3, lines 38-54] a storage device that includes a CPU and that would benefit from the ability to implement a full or partial reset of CPU (executing reset of a first or second type) and/or integrated peripheral device control parameters of the storage device.
As per claim 8: The method of claim 1, wherein suspending further comprises: suspending, based on detecting the crash, processing commands, via the processor of the storage device, from the host through the connection.
Freeman discloses [0021] normal access to the device by the host computer is prevented and normal operations of the device are suspended so that the self-diagnosis procedure can be completed in relative isolation.
As per claim 9: The method of claim 1, further comprising: receiving a reset operation from the host; and resetting a storage interface based on receiving the reset operation from the host.
Eny discloses [col. 9, lines 8-21] the CPU controller determines that a user has requested a reset and the CPU controller clears all CPU/core and peripheral unit control parameters of the device.
As per claim 10: The method of claim 9, wherein: the reset operation comprises a controller reset; and resetting the storage interface comprises resetting a controller in the storage interface.
Eny discloses [col. 9, lines 8-21] the CPU controller determines that a user has requested a reset and the CPU controller clears all CPU/core and peripheral unit control parameters of the device.
As per claims 11, 14, 15, and 18: Although claims 11, 14, 15, and 18 are directed towards a device claim, they are rejected under the same rationale as the method claims 1, 4, 5, and 8 above.
Claims 2, 3, 6, 7, 12, 13, 16, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Freeman in view of Eny and further in view of Grosz and further in view of Arroyo et al. (US 2017/0116085 A1).
As per claim 2: The method of claim 1, wherein recovering from the crash of the storage device further comprises: initiating a second restart operation of the processor of the storage device.
Freeman, Eny, and Grosz disclose recovering from a storage device crash with a partial reset or a full reset, but fail to explicitly disclose initiating a second restart operation of the storage device. Arroyo discloses a similar method, which further teaches [0022] a PCI includes a warm reset mode and a full reset mode (similar to Eny). A warm reset greatly speeds the time for the PHB to recover from an error. When initialization of the PHB after a warm reset is not successful, a full reset is performed (second restart operation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Freeman, Eny, and Grosz with that of Arroyo. One would have been motivated to initiate a second restart operation because a warm reset could have been unsuccessful, requiring a full reset instead [Arroyo; 0022].
As per claim 3: The method of claim 2, wherein recovering from the crash of the storage device further comprises: transferring, by the processor of the storage device, data from a first medium of the storage device to a second medium of the storage device.
Eny discloses [col. 4, lines 15-35] transferring data from a first memory storage device to a second memory storage device.
As per claim 6: The method of claim 4, wherein recovering from the crash of the storage device further includes processing an event of a second type at a storage interface.
Freeman and Eny disclose recovering from a storage device crash with a partial reset or a full reset, but fail to explicitly disclose initiating a second restart operation of the storage device. Arroyo discloses a similar method, which further teaches [0022] a PCI includes a warm reset mode and a full reset mode (similar to Eny). A warm reset greatly speeds the time for the PHB to recover from an error. When initialization of the PHB after a warm reset is not successful, a full reset is performed (second restart operation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Freeman and Eny with that of Arroyo. One would have been motivated to initiate a second restart operation because a warm reset could have been unsuccessful, requiring a full reset instead [Arroyo; 0022].
As per claim 7: The method of claim 6, wherein the event of the second type is one of a port-level reset, a function-level reset, a control transaction, or a memory transaction.
Arroyo discloses [0022] the event of the second type is a function-level reset.
As per claims 12, 13, 16, and 17: Although claims 12, 13, 16, and 17 are directed towards a device claim, they are rejected under the same rationale as the method claims 2, 3, 6, and 7 above.
As per claim 19: Although claim 19 is directed towards a medium claim, it is rejected under the same rationale as the combination of method claims 1 and 2 above and is obvious variant of the combination of method claims 1 and 2 above.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Freeman in view of Eny and further in view of Grosz and further in view of Arroyo and further in view of Lucas.
As per claim 20: The non-transitory computer readable storage medium of claim 19, wherein recovering from the crash of the storage device further comprises:
reloading a portion of firmware for the management processor of the storage device based on initiating the first restart operation of the management processor of the storage device.
Freeman and Eny disclose performing full or partial reset and resume from a crash of a storage device to fully operational state, but fail to explicitly disclose reloading a portion of firmware for the processor of the storage device based on first restart. Lucas discloses a similar method, which further teaches [col. 12, lines 15-30] volatile and non-volatile memory for storing data, optionally including basic firmware that includes boot software to allow memory controller to boot firmware from a non-volatile firmware store (e.g. firmware store 217). This indicates that the basic firmware (element 272) is a distinct portion of the processor’s code that manages the boot process. It is the agent doing the reloading, meaning it is not being reloaded itself. Lucas further discloses [col. 12, lines 60-67] a revert signal indicates to basic firmware which version of firmware to load from firmware store 217 at power-up. For example, if the revert signal is logically true, basic firmware loads the original production level firmware. This indicates the firmware store contains the reloadable portions (versions). The basic version is the static version. By loading the original production level firmware, the system is reloading only the operational portion of the firmware to process host commands, while the basic firmware portion remains resident to facilitate this action.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Freeman, Eny, Grosz, and Arroyo with that of Lucas. One would have been motivated to reload a portion of firmware because it allows to load multiple versions of firmware [col. 12, lines 50-60].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11, and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
· US 10,481,805 B1 – Sahin discloses preventing timeouts of I/O requests at a data storage system by responding to the host at a predetermined time before timeout, which will prevent the timeout from occurring and may cause the host system to retry the I/O operation.
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/JIGAR P PATEL/Primary Examiner, Art Unit 2114