Prosecution Insights
Last updated: August 06, 2026
Application No. 18/650,031

CHIP PAD SURFACE LEVELING DEVICE

Non-Final OA §103
Filed
Apr 29, 2024
Priority
Sep 27, 2023 — CN 202311264079.4
Examiner
OMGBA, ESSAMA
Art Unit
Tech Center
Assignee
Shine Optics Technology Company Limited
OA Round
1 (Non-Final)
59%
Grant Probability
Moderate
1-2
OA Rounds
1y 2m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 59% of resolved cases
59%
Career Allowance Rate
481 granted / 811 resolved
-0.7% vs TC avg
Strong +33% interview lift
Without
With
+33.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
15 currently pending
Career history
826
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
60.2%
+20.2% vs TC avg
§102
18.2%
-21.8% vs TC avg
§112
18.3%
-21.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 811 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Araki et al. (JP04116832) in view of Iyer (US2015/0087082), Gabriel et al. (US Patent 4,344,160) and Hu et al. (US Patent 4,908,328). With regard to claims 1 and 8, Araki et al. discloses a chip pad leveling device (title) comprising a signal control module (system that moves and control the different part of the chip pad leveling device of Araki et al., a leveling head module 5’ (fig. 1) configured to be electrically connected to the signal control module (this is inherent for the leveling head module to be able to automatically move as disclosed). Araki et al. does not disclose a temperature control module configured to be electrically connected to the signal control module however, it is known to use a temperature control module when processing semiconductor devices in order to selectively heat the semiconductor devices so as to provide necessary heat in order to facilitate processing as attested by Iyer, see abstract. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have incorporated a temperature control module in the chip pad leveling device of Khoury et al., in light of the teaching of Iyer, in order to provide necessary heat in order to facilitate the leveling process. Regarding the recitation of the carrying module being a glass carrying module, Applicant should note that it is Known to use a glass platen to flatten silicon wafer surfaces as attested by Gabriel et al., see column 3, lines 47-48. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have incorporated a glass platen in the leveling head module of Araki et al./Iyer, in light of the teachings of Gabriel et al., as is known in the art. Further, it is known to flatten surfaces of wafers to a mirror finish (which is, as one of ordinary skill would understand, is to a surface roughness of less than 1 µm) as attested by Hu et al., see column 3, lines 7-9. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have used a glass platen with a surface that could impart a mirror finish to the leveled surfaces of the bumps of Araki et al./Iyer/Gabriel et al., in light of the teachings of Hu et al., as is known in the art. Regarding claims 2 and 9, see stage 3 in figure 1 of Araki et al. and the English machine translation. Further, Official Notice is taken in that surface roughness detection modules are old and well known in the art of processing semiconductors and it would have been obvious to incorporate one in the chip pad surface leveling device of Araki et al./Iyer/Gabriel et al./Hu et al. in order to assess the surface roughness of the leveled bumps. Regarding claims 3 and 10, see leveling head 5’ of Araki et al. and the English machine translation of Araki et al. Applicant should note that the chip pad surface leveling device of Araki et al./Iyer/Gabriel et al./Hu et al. is capable of being used as recited in the claim. Regarding claim 4, Applicant should note that it is obvious that a pressure sensing module would have to be included in the chip pad surface leveling device of Araki et al./Iyer/Gabriel et al./Hu et al. in order to ensure that the proper pressure is being applied to the chip pads and avoid damaging the chip pad with excess pressure or not appropriately leveling the chip pads with not enough pressure. Regarding claim 5, Applicant should note that the particular temperature or pressure to be applied to the chip pads will depend on the material of the chip pads. Regarding claims 6 and 7, Applicant should note that the recited type of chips lends no patentable weight to the chip pad leveling device. Further, the device of Araki et al./Iyer/Gabriel et al./Hu et al. is capable of being used with the recited type of chips. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESSAMA OMGBA whose telephone number is (469)295-9278. The examiner can normally be reached Monday to Thursday from 10:00 AM to 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alford Kindred can be reached at 571-272-4037. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ESSAMA OMGBA/ Supervisory Patent Examiner, Art Unit 3746
Read full office action

Prosecution Timeline

Apr 29, 2024
Application Filed
Jul 24, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
59%
Grant Probability
92%
With Interview (+33.1%)
3y 6m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 811 resolved cases by this examiner. Grant probability derived from career allowance rate.

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