DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 15 is objected to because of the following informalities: Claim 15, “a first transistor” at the end of line 8 and “a second transistor” in lines 10-11 should be -- the first transistor -- and -- the second transistor --. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 8-10, 12, 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen et al. in view of Kim et al. (KR 20190011494 A and Kim hereinafter).
Regarding claim 1, Nguyen discloses driving circuit [fig. 3] for a power transistor [51], the driving circuit comprising: a gate driving circuit [32B] configured to output a driving voltage signal [vdr1] and a pulse width modulation signal [PWM]; a controlling circuit [comprising 36/35/52/53] comprising: a voltage controller [35/36] configured to output a controlling signal [FLT/ID]; a first transistor [52] coupled to the gate driving circuit and selectively turned on or off according to the pulse width modulation signal [par. 0020-024]; and a second transistor [53] coupled to the gate driving circuit and the voltage controller, and selectively turned on or off according to the pulse width modulation signal and the controlling signal; the power transistor coupled to the gate driving circuit and the controlling circuit, and controlled by the driving voltage signal [par. 0020-0027]; wherein in response to determining that the first transistor is turned on or both the first transistor and the second transistor are turned on, the driving voltage signal is pulled to a target voltage level [par. 0025-0027]. Nguyen does not explicitly disclose the gate driving circuit configured to output the pulse width modulation signal.
However, Kim discloses [see fig. 2] a gate driving circuit [100] configured to output a pulse width modulation signal [output 120 through 134]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Nguyen as taught in Kim in order to control the power transistor.
Regarding claim 2, Nguyen in view of Kim discloses [fig. 3] wherein the gate driving circuit comprises: a pulse width modulation controller [external to output PWM, fig.3, Nguyen ref./120, fig. 2, Kim ref.] configured to generate the pulse width modulation signal; and a gate driver [32B, fig.3, Nguyen ref./130, Kim ref] electrically connected to the pulse width modulation controller and converting the pulse width modulation signal into the driving voltage signal.
Regarding claim 3, Nguyen in view of Kim discloses [fig. 3] wherein, the first transistor comprises: a first gate terminal [24] coupled to the pulse width modulation controller; a first drain terminal [25] electrically connected to the gate driver and a gate terminal of the power transistor [23]; and a first source terminal [28] forming a kelvin connection with a source terminal of the power transistor [22]; and the second transistor comprises: a second gate terminal [26] coupled to the pulse width modulation controller and the voltage controller; a second drain terminal [27] electrically connected to the gate driver and the gate terminal of the power transistor; and a second source terminal [29] forming the kelvin connection with the source terminal of the power transistor.
Regarding claim 5, Nguyen in view of Kim discloses [fig. 3] wherein the voltage controller captures a feedback voltage signal [Vds] from the power transistor and determines whether a slope of the feedback voltage signal is greater than a threshold value [Vth] to generate a signal confirmation result [FLT]; wherein in response to determining that the signal confirmation result is yes, the controlling signal is 1; wherein in response to determining that the signal confirmation result is no, the controlling signal is 0 [par. 0026-0031].
Regarding claim 8, Nguyen discloses driving circuit [fig. 3] for a power transistor [51], the driving circuit comprising: a gate driving circuit [32B] configured to output a driving voltage signal [vdr1], a pulse width modulation signal [PWW] and a controlling signal; a controlling circuit [FLT/ID] comprising: a first transistor [52] coupled to the gate driving circuit and selectively turned on or off according to the pulse width modulation signal [par. 0020-024]; and a second transistor [53] coupled to the gate driving circuit and selectively turned on or off according to the pulse width modulation signal and the controlling signal [par. 0020-0027]; the power transistor [51] coupled to the gate driving circuit [32B] and the controlling circuit [35/36], and controlled by the driving voltage signal; wherein in response to determining that the first transistor is turned on or both the first transistor and the second transistor are turned on, the driving voltage signal is pulled to a target voltage level [par. 0025-0027]. Nguyen does not explicitly disclose the gate driving circuit configured to output the pulse width modulation signal.
However, Kim discloses [see fig. 2] a gate driving circuit [100] configured to output a pulse width modulation signal [output 120 through 134]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Nguyen as taught in Kim in order to control the power transistor.
Regarding claim 9, Nguyen in view of Kim discloses [fig. 3] wherein the gate driving circuit comprises: a pulse width modulation controller [external to output PWM, fig.3, Nguyen ref./120, fig. 2, Kim ref.] configured to generate the pulse width modulation signal; and a gate driver [32B, fig.3, Nguyen ref./130, Kim ref] electrically connected to the pulse width modulation controller and converting the pulse width modulation signal into the driving voltage signal.
Regarding claim 10, Nguyen in view of Kim discloses [fig. 3] wherein, the first transistor comprises: a first gate terminal [24] coupled to the pulse width modulation controller; a first drain terminal [25] electrically connected to the gate driver and a gate terminal of the power transistor [23]; and a first source terminal [28] forming a kelvin connection with a source terminal of the power transistor [22]; and the second transistor comprises: a second gate terminal [26] coupled to the pulse width modulation controller; a second drain terminal [27] electrically connected to the gate driver and the gate terminal of the power transistor; and a second source terminal [29] forming the kelvin connection with the source terminal of the power transistor.
Regarding claim 12, Nguyen in view of Kim discloses [fig. 3] wherein the gate driving circuit captures a feedback voltage signal [Vds] from the power transistor and determines whether a slope of the feedback voltage signal is greater than a threshold value [Vth] to generate a signal confirmation result [FLT]; wherein in response to determining that the signal confirmation result is yes, the controlling signal is 1; wherein in response to determining that the signal confirmation result is no, the controlling signal is 0 [par. 0026-0031].
Regarding claim 15, Nguyen discloses a controlling method of driving circuit [fig. 3] for a power transistor [51], the controlling method comprising: a signal outputting step comprising: configuring a gate driving circuit [32B] to output a driving voltage signal [vdr1] and a pulse width modulation signal [PWM]; and configuring one of the gate driving circuit and a voltage controller [35/36] to output a controlling signal [FLT/ID]; a first transistor controlling step [step controlling 52] comprising controlling a first transistor [52] to selectively turn on or off according to the pulse width modulation signal [par. 0020-024]; a second transistor controlling step [step controlling 53] comprising controlling a second transistor [53] to selectively turn on or off according to the pulse width modulation signal and the controlling signal [par. 0020-0027]; and a power transistor [51] controlling step comprising controlling the power transistor according to the driving voltage signal; wherein in response to determining that the first transistor is turned on or both the first transistor and the second transistor are turned on, the driving voltage signal is pulled to a target voltage level [par. 0025-0027]. Nguyen does not explicitly disclose the gate driving circuit configured to output the pulse width modulation signal.
However, Kim discloses [see fig. 2] a gate driving circuit [100] configured to output a pulse width modulation signal [output 120 through 134]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Nguyen as taught in Kim in order to control the power transistor.
Regarding claim 16, Nguyen in view of Kim discloses [fig. 3] wherein the gate driving circuit comprises a pulse width modulation controller [external to output PWM, fig.3, Nguyen ref./120, fig. 2, Kim ref.] and a gate driver [32B, fig.3, Nguyen ref./130, Kim ref], and the signal outputting step further comprises: configuring the pulse width modulation controller to generate the pulse width modulation signal [PWM]; and configuring the gate driver to convert the pulse width modulation signal into the driving voltage signal [vdr1].
Regarding claim 17, Nguyen in view of Kim discloses [fig. 3] wherein in the signal outputting step, the one of the gate driving circuit and the voltage controller captures a feedback voltage signal [Vds] from the power transistor and determines whether a slope of the feedback voltage signal is greater than a threshold to generate [Vth] a signal confirmation result [FLT]; wherein in response to determining that the signal confirmation result is yes, the controlling signal is 1; wherein in response to determining that the signal confirmation result is no, the controlling signal is 0 [par. 0026-0031].
3. Claims 6-7, 13-14 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen et al. in view of Kim et al.
Regarding claims 6-7, 13-14 and 18-19, Nguyen in view of Kim discloses all the features with respect to claims 1, 8 and 15 as outlined above. Nguyen in view of Kim does not explicitly disclose wherein the first transistor and the second transistor are both an enhancement mode metal-oxide-semiconductor field effect transistor (MOSFET) or wherein the power transistor is a high electron mobility transistor (HEMT). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace the transistors of Nguyen /Kim with an enhancement mode metal-oxide-semiconductor field effect transistor/ a high electron mobility transistor because such a modification would have been merely a replacement with a well-known, art-recognized functionally equivalent transistor device.
Allowable Subject Matter
Claims 4 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to METASEBIA T RETEBO whose telephone number is (571)272-9299. The examiner can normally be reached M - F 8:30 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached at 571-272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/METASEBIA T RETEBO/Primary Examiner, Art Unit 2842