DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 and 3 –13 are pending, and claims 1 and 13 are independent claims.
Response to Arguments
Applicant's arguments, see Arguments pages 6-9, filed on 04/22/2026, with respect to 35 USC § 102 and 35 USC § 103 claim rejections have been fully considered but they are not persuasive.
The Applicant argues that a "claim is anticipated only if each and every element as set forth in the claim is found, either expressly or inherently described, in a single prior art reference" and Mortenson does not meet this stringent requirement (Arguments, page 6).
The Examiner respectfully disagrees. Mortenson does actually meet the stringent requirement that a "claim is anticipated only if each and every element as set forth in the claim in this single prior art reference, and each of the limitations of those claims under 35 USC § 102 rejections have been mapped using this single Mortenson reference.
After indicating that their amended Claim 1 recites "a first memory, storing the first audio data and a first program code" and "a second program code in a second memory," and also indicating that their claimed invention thus establishes a dual-memory hardware architecture in which a first memory stores both first audio data and a first program code, and a distinct second memory stores a second program code as well as second audio data, the Applicant argues that Mortensen fails to disclose such claimed "first memory" that stores both the first audio data and a first program code. The Applicant argues that amended claim 1 recites "a first memory, storing the first audio data and a first program code" and "a second program code in a second memory" and the claimed invention establishes a dual-memory hardware architecture in which a first memory stores both first audio data and a first program code, and a distinct second memory stores a second program code as well as second audio data. The Applicant argues that this dual-memory architecture is fundamental to the claimed invention and is entirely absent from Mortensen. Another but similar argument of the Applicant is that the second memory serves as a triple function of storing a second program, receiving first audio data transferred from first memory and storing subsequently generated second audio data (Arguments, page 7).
The Examiner respectfully disagrees. Mortensen teaches "first memory" that stores both the first audio data and a first program code. Mortensen teaches about preferred embodiment of the microphone circuit assembly comprises a circular speech data buffer configured for storage of consecutive speech segments representing predetermined time periods of the microphone signal samples, the speech being the audio data stored in memory. Furthermore, Mortensen teaches that the microphone circuit assembly may comprise a floating point converter operatively coupled between an output of the analog-to-digital converter and an input of the speech feature extractor. The microphone circuit assembly comprises a circular speech data buffer configured for storage of consecutive speech segments representing predetermined time periods of the microphone signal samples. The circular speech data buffer may reside in a suitable data memory area or segment of the microphone circuit assembly such as a register file or SRAM data memory area. Thus, circular speech data buffer is like the first memory in the instant application. The size or capacity of the circular speech data buffer varies according to its intended application. In some embodiments, the circular speech data buffer functions only as a temporary storage area for the speech feature extractor allowing blocks of microphone signal samples to be accumulated and temporarily stored before subsequent processing in a block based filter bank algorithm such as a MFCC filter bank. In these embodiments the circular speech data buffer may be sized to hold between 256 and 1024 microphone signal samples. The circular speech data buffer may reside in a suitable data memory area or segment of the microphone circuit assembly such as a register file or SRAM data memory area. In Mortensen, according to another preferred embodiment of the microphone circuit assembly the microphone preamplifier and analog-to-digital converter are operative in at least a first power mode and a second power mode. The first power mode has a first power consumption and the microphone signal samples are generated at the first predetermined sample rate with a first dynamic range. The second power mode has a second power consumption and the microphone signal samples are generated with a second dynamic range at a second predetermined sample rate. The second dynamic range is larger than the first dynamic range and the second power consumption is larger than the first power consumption. This embodiment allows the microphone circuit assembly to be operated at different microphone signal quality or performance levels with corresponding power consumption levels depending on a system state. The first power mode may be a low-power mode or reduced performance mode of the microphone circuit assembly suitable for wake-up system applications as discussed above. The controller of the microphone circuit assembly may be configured to switch from the first power mode to the second power mode in response to the recognition of the target word or phrase. In a preferred embodiment, the controller is further adapted to initiate transmission of the microphone signal samples through the data communication interface in response to the recognized target word or phrase. Hence, the microphone circuit assembly may be configured to interrupt the transmission of the microphone signal samples in the first power mode to minimize power consumption. The second power mode may be a nominal performance mode in which the microphone signal samples are generated with a larger dynamic range and/or higher sampling rate than in the first power mode/low-power mode albeit at the expense of increased power consumption of the microphone preamplifier and analog-to-digital converter. A low power consumption of the microphone circuit assembly while the associated external application processor and system reside in sleep-mode awaiting the predetermined target word or phrase to wake-up and switch to normal operation represents one distinct advantage of this switchable power mode feature for voice activated system power-up applications. Mortensen teaches the limitation of a first memory, storing the first audio data and a first program code, as well as a second program code in a second memory, in fact multiple program codes in the second memory. The microphone circuit assembly comprises a circular speech data buffer configured for storage of consecutive speech segments representing predetermined time periods of the microphone signal samples. The circular speech data buffer may reside in a suitable data memory area or segment of the microphone circuit assembly such as a register file or SRAM data memory area… as well as execution of a suitable speech recognition application or program… The Digital Signal Processing system or DSP system comprises a microphone circuit assembly according to any of the above-described embodiments thereof. The DSP system further comprises a programmable Digital Signal Processor (DSP) comprising a program memory space for storage of respective sets of executable program instructions of a plurality of predetermined application programs. That is, the microphone circuit assembly comprises a memory [i.e., first memory] holding the audio/speech data as well as processing application of speech recognition. The second memory involves the DSP with sets of executable program instructions of a plurality of predetermined application programs (Mortensen, Para 0014-0015 and 0021-0025).
Applicant argues that Mortensen fails to disclose the limitations of "switched from operating in the first mode to operating in a second mode in response to an interrupt signal from the audio generator circuit so as to execute a second program code in a second memory, in order to determine whether the first audio data stored in the first memory includes a human voice signal." (1) Different trigger mechanism. The claim requires an interrupt signal from the audio generator circuit (an external trigger). Mortensen's controller switches modes "in response to the recognition of the target word or phrase" (paragraphs [0014]-[0015])-an internally generated trigger, with signal flowing outward (INTO -> INTDSP), opposite to the claimed direction. (2) No switching between program codes in different memories. Mortensen's controller is a hardware-based decision circuit. The concept of a single processor transitioning from executing a first program code in a first memory to executing a second program code in a second memory is entirely absent from Mortensen. (3) Opposite purpose of mode switching. In the claimed invention, the processor switches to the second mode to perform voice detection. In Mortensen, the mode switch occurs after keyword recognition is already complete, for the purpose of improving audio quality-the opposite operational sequence. The Applicant further argues that once human voice is detected, the processor controls the first memory to transfer the first audio data to the second memory, and subsequently the audio processing circuit stores the second audio data into the same second memory. This creates a consolidated data set in the second memory comprising both pre-trigger (first audio data) and post-trigger (second audio data) audio for integrated processing. Mortensen uses a circular buffer for continuous data storage. While Mortensen mentions transmitting data to an external processor (paragraph 0021), it does not describe an internal transfer process within the VAD device between two memories to consolidate "pre- trigger" (first data) and "post-trigger" (second data) audio for processing (Arguments, page 7-8).
The Examiner respectfully disagrees. Mortensen teaches the limitations stating that the microphone circuit assembly the microphone preamplifier and analog-to-digital converter are operative in at least a first power mode and a second power mode. The first power mode has a first power consumption and the microphone signal samples are generated at the first predetermined sample rate with a first dynamic range. The second power mode has a second power consumption and the microphone signal samples are generated with a second dynamic range at a second predetermined sample rate. The second dynamic range is larger than the first dynamic range and the second power consumption is larger than the first power consumption. This embodiment allows the microphone circuit assembly to be operated at different microphone signal quality or performance levels with corresponding power consumption levels depending on a system state. The first power mode may be a low-power mode or reduced performance mode of the microphone circuit assembly suitable for wake-up system applications as discussed above. The controller of the microphone circuit assembly may be configured to switch from the first power mode to the second power mode in response to the recognition of the target word or phrase. In a preferred embodiment, the controller is further adapted to initiate transmission of the microphone signal samples through the data communication interface in response to the recognized target word or phrase. Hence, the microphone circuit assembly may be configured to interrupt the transmission of the microphone signal samples in the first power mode to minimize power consumption. The second power mode may be a nominal performance mode in which the microphone signal samples are generated with a larger dynamic range and/or higher sampling rate than in the first power mode/low-power mode albeit at the expense of increased power consumption of the microphone preamplifier and analog-to-digital converter. A low power consumption of the microphone circuit assembly while the associated external application processor and system reside in sleep-mode awaiting the predetermined target word or phrase to wake-up and switch to normal operation represents one distinct advantage of this switchable power mode feature for voice activated system power-up applications. Mortensen discloses microphone circuit assembly that comprises a circular speech data buffer configured for storage of consecutive speech segments representing predetermined time periods of the microphone signal samples. The circular speech data buffer may reside in a suitable data memory area or segment of the microphone circuit assembly such as a register file or SRAM data memory area. The size or capacity of the circular speech data buffer varies according to its intended application. In some embodiments, the circular speech data buffer functions only as a temporary storage area for the speech feature extractor allowing blocks of microphone signal samples to be accumulated and temporarily stored before subsequent processing in a block based filter bank algorithm such as a MFCC filter bank. In these embodiments the circular speech data buffer may be sized to hold between 256 and 1024 microphone signal samples. In other embodiments, the circular speech data buffer has capacity to hold relatively large consecutive segments of the microphone signal samples for example microphone signal samples representing a time period larger than one of 500 ms and 1 second. These time periods correspond to 8.000 and 16.000 microphone signal samples, respectively, at a sample rate of 16 kHz. The large storage capacity of the circular speech data buffer is utilized in advantageous embodiment of the invention where the controller is configured to, in response to a recognized target word or target phrase, transmitting a speech segment comprising the recognized target word or phrase from the circular speech data buffer, which is considered as the first memory, to the … application processor through the data communication interface. a speech segment comprising the recognized target word or phrase from the circular speech data buffer to the external application processor through the data communication interface. This feature allows the external application processor to perform an independent verification of the presence of th (Mortensen, para 0014-0015 and 21).
The Applicant still further argues that Mortensen fails to disclose the limitations of "the processor further controls the first memory to transfer the first audio data to the second memory, and the audio processing circuit further stores second audio data to the second memory, wherein the audio processing circuit generates the second audio data according to the audio signal after generating the first audio data" (Arguments, page 8).The Examiner respectfully disagrees. Mortensen teaches the limitations of "the processor further controls the first memory to transfer the first audio data to the second memory, and the audio processing circuit further stores second audio data to the second memory, wherein the audio processing circuit generates the second audio data according to the audio signal after generating the first audio data." Mortensen teaches the microphone circuit assembly comprises a circular speech data buffer configured for storage of consecutive speech segments. The circular speech data buffer may reside in a suitable data memory area or segment of the microphone circuit assembly such as a register file or SRAM data memory area. The size or capacity of the circular speech data buffer varies according to its intended application. In some embodiments, the circular speech data buffer functions only as a temporary storage area for the speech feature extractor allowing blocks of microphone signal samples to be accumulated and temporarily stored before subsequent processing in a block based filter bank algorithm such as a MFCC filter bank. In these embodiments the circular speech data buffer may be sized to hold between 256 and 1024 microphone signal samples. In other embodiments, the circular speech data buffer has capacity to hold relatively large consecutive segments of the microphone signal samples for example microphone signal samples representing a time period larger than one of 500 ms and 1 second. The large storage capacity of the circular speech data buffer is utilized in advantageous embodiment of the invention where the controller is configured to, in response to a recognized target word or target phrase, transmitting a speech segment comprising the recognized target word or phrase from the circular speech data buffer to the external application processor through the data communication interface… the programmable DSP where the data communication interface is configured for receipt of microphone signal samples transmitted by the microphone circuit assembly subsequently to issuance of the recognition signal; [“transmitted…audio” as “transferred ..audio” ]; The present embodiment of the circular speech data buffer 214 comprises a second output 215 which is coupled to the bi-directional data communication interface 222 or communication interface. The communication interface 222 is configured for transmission of certain portions of the digital microphone samples, for example comprising selected segments of stored speech... After the decision circuit 220 has recognized the target word or phrase and notified the application processor through the previously discussed recognition signal INT_DSP, the controller 226 may be adapted to start transmitting generated microphone signal samples immediately after the above-described selected speech segments (Mortensen, para 0021-0026 and 0040).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 10-11 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mortensen Pat App No. US 20140257813 A1 (Mortensen).
Regarding Claim 1. Mortensen discloses a voice activity detection device, comprising:
an audio processing circuit, processing an audio signal from an audio generator circuit to generate first audio data (Mortensen, Para 0007, A first aspect of the invention relates to a microphone circuit assembly for an external application processor, comprising: a microphone preamplifier comprising an input terminal for receipt of a microphone signal, an analog-to-digital converter configured for receipt of an output signal of the microphone preamplifier and generation of corresponding microphone signal samples having a first predetermined number of bits at a first predetermined sample rate, a speech feature extractor configured for receipt and processing of predetermined blocks of the microphone signal samples to extract speech feature vectors representing speech features of the microphone signal samples);
a first memory, storing the first audio data and a first program code (Mortensen, Para 0021, another preferred embodiment of the microphone circuit assembly comprises a circular speech data buffer configured for storage of consecutive speech segments representing predetermined time periods of the microphone signal samples. The circular speech data buffer may reside in a suitable data memory area or segment of the microphone circuit assembly such as a register file or SRAM data memory area); and
a processor, executing the first program code to operate in a first mode, and switched from operating in the first mode to operating in a second mode in response to an interrupt signal from the audio generator circuit so as to execute a second program code in a second memory, in order to determine whether the first audio data stored in the first memory includes a human voice signal (Mortensen, Para 0014-0015, According to another preferred embodiment of the microphone circuit assembly the microphone preamplifier and analog-to-digital converter are operative in at least a first power mode and a second power mode. The first power mode has a first power consumption and the microphone signal samples are generated at the first predetermined sample rate with a first dynamic range. The second power mode has a second power consumption and the microphone signal samples are generated with a second dynamic range at a second predetermined sample rate. The second dynamic range is larger than the first dynamic range and the second power consumption is larger than the first power consumption. This embodiment allows the microphone circuit assembly to be operated at different microphone signal quality or performance levels with corresponding power consumption levels depending on a system state. The first power mode may be a low-power mode or reduced performance mode of the microphone circuit assembly suitable for wake-up system applications as discussed above. The controller of the microphone circuit assembly may be configured to switch from the first power mode to the second power mode in response to the recognition of the target word or phrase. In a preferred embodiment, the controller is further adapted to initiate transmission of the microphone signal samples through the data communication interface in response to the recognized target word or phrase. Hence, the microphone circuit assembly may be configured to interrupt the transmission of the microphone signal samples in the first power mode to minimize power consumption. The second power mode may be a nominal performance mode in which the microphone signal samples are generated with a larger dynamic range and/or higher sampling rate than in the first power mode/low-power mode albeit at the expense of increased power consumption of the microphone preamplifier and analog-to-digital converter. A low power consumption of the microphone circuit assembly while the associated external application processor and system reside in sleep-mode awaiting the predetermined target word or phrase to wake-up and switch to normal operation represents one distinct advantage of this switchable power mode feature for voice activated system power-up applications; Mortensen, Para 0025-0029, The Digital Signal Processing system or DSP system comprises a microphone circuit assembly … the predetermined application program stored in program memory of the programmable DSP comprises a speech recognition application with a set of executable program instructions configured to when executed; [“the DSP system” as “second memory”; “speech recognition application” as “the program to be executed”]),
wherein power consumption of the processor operating in the first mode is lower than that in the second mode (Mortensen, Para 0008-0009, This feature allows the external application processor to reside in a power savings mode such as a power-down or sleep-mode without processing of the incoming microphone signal until receipt of the recognition signal… This feature leads to a beneficial reduction of computational load and power consumption of the external application processor).
wherein when the processor determines that the first audio data includes the human voice signal, the processor further controls the first memory to transfer the first audio data to the second memory, and the audio processing circuit further stores second audio data to the second memory, wherein the audio processing circuit generates the second audio data according to the audio signal after generating the first audio data. (Mortensen, para 0022, The microphone circuit assembly may comprise a floating point converter operatively coupled between an output of the analog-to-digital converter and an input of the speech feature extractor, [i.e., equivalent to the first memory]), the processor further controls the first memory to transfer the first audio data to the second memory, and the audio processing circuit further stores second audio data to the second memory, wherein the audio processing circuit generates the second audio data according to the audio signal after generating the first audio data (Mortensen, para 0021, the microphone circuit assembly comprises a circular speech data buffer configured for storage of consecutive speech segments representing predetermined time periods of the microphone signal samples. The circular speech data buffer may reside in a suitable data memory area or segment of the microphone circuit assembly such as a register file or SRAM data memory area. The size or capacity of the circular speech data buffer varies according to its intended application. In some embodiments, the circular speech data buffer functions only as a temporary storage area for the speech feature extractor allowing blocks of microphone signal samples to be accumulated and temporarily stored before subsequent processing in a block based filter bank algorithm such as a MFCC filter bank. In these embodiments the circular speech data buffer may be sized to hold between 256 and 1024 microphone signal samples. In other embodiments, the circular speech data buffer has capacity to hold relatively large consecutive segments of the microphone signal samples for example microphone signal samples representing a time period larger than one of 500 ms and 1 second. These time periods correspond to 8.000 and 16.000 microphone signal samples, respectively, at a sample rate of 16 kHz. The large storage capacity of the circular speech data buffer is utilized in advantageous embodiment of the invention where the controller is configured to, in response to a recognized target word or target phrase, transmitting a speech segment comprising the recognized target word or phrase from the circular speech data buffer to the external application processor through the data communication interface; “selected speech segment transmitted by the microphone circuit assembly 201 through the bi-directional data interface 422; … the programmable DSP where the data communication interface is configured for receipt of microphone signal samples transmitted by the microphone circuit assembly subsequently to issuance of the recognition signal”; “transmitted…audio” as “transferred ..audio”]; Mortensen, para 0040, The present embodiment of the circular speech data buffer 214 comprises a second output 215 which is coupled to the bi-directional data communication interface 222 or communication interface. The communication interface 222 is configured for transmission of certain portions of the digital microphone samples, for example comprising selected segments of stored speech... After the decision circuit 220 has recognized the target word or phrase and notified the application processor through the previously discussed recognition signal INT_DSP, the controller 226 may be adapted to start transmitting generated microphone signal samples immediately after the above-described selected speech segments).
Regarding Claim 3. Mortensen discloses the voice activity detection device according to claim 2, wherein the processor further determines, according to the first audio data and the second audio data in the second memory, whether the first audio data and the second audio data include a keyword message (para 0021, The large storage capacity of the circular speech data buffer is utilized in advantageous embodiment of the invention where the controller is configured to, in response to a recognized target word or target phrase, transmitting a speech segment comprising the recognized target word or phrase from the circular speech data buffer to the external application processor through the data communication interface. This feature allows the external application processor to perform an independent verification of the presence of the target word or a target phrase in the transmitted speech segment for example by execution of a suitable speech recognition application or program leading to numerous benefits as described below in connection with the preferred embodiments of the invention; [“recognized target word or target phrase” as “a keyword message”]).
Regarding Claim 10. Mortensen discloses the voice activity detection device according to claim 1, further comprising:
a clock generator circuit, generating a first clock signal according to a reference clock signal (para 0055, In an alternative embodiment, the microphone circuit assembly 201 comprises two independent clocking systems. A first clock system is based on an internal self-contained clock oscillator and generator which supply the master clock signal when the microphone circuit assembly 201 operates in its low power mode awaiting the predetermined voice or speech command. This relaxes clock signal generation capabilities of the software programmable DSP 402 during system power down),
wherein when the processor operates in the first mode, the clock generator circuit generates the first clock signal for the audio processing circuit, and the audio processing circuit processes the audio signal according to the first clock signal so as to generate the first audio data (0053] FIG. 4 is a schematic drawing of a Digital Signal Processing System 400 comprising the first embodiment of the present microphone circuit assembly 201 as illustrated in detail on FIG. 2 in accordance with separate aspect of the present invention…The exchange of data through the bi-directional data interface is synchronized to a serial data clock signal supplied by the S_CLK terminal of the programmable DSP 402…the software programmable DSP 402 is configured a master device for the microphone circuit assembly 201 and supplies a master clock signal thereto through terminals or pads M_CLK and M_CLKI. The master clock signal supplied to the microphone circuit assembly 201 may have a frequency between 1.0 MHz and 5.0 MHz. The master clock signal may be used as a clock source for the previously discussed sigma-delta analog-to-digital converter of the signal conditioner 204 and to clock digital logic of the speech recognition unit 206.).
Regarding Claim 11. Mortensen discloses the voice activity detection device according to claim 1, further comprising:
a clock generator circuit, generating a first clock signal according to a reference clock signal (para 0055, In an alternative embodiment, the microphone circuit assembly 201 comprises two independent clocking systems. A first clock system is based on an internal self-contained clock oscillator and generator which supply the master clock signal when the microphone circuit assembly 201 operates in its low power mode awaiting the predetermined voice or speech command. This relaxes clock signal generation capabilities of the software programmable DSP 402 during system power down),
wherein when the processor operates in the first mode, the clock generator circuit does not generate the first clock signal, such that the audio processing circuit does not generate the first audio data (para 0008, The sleep-mode of the external application processor is preferably a mode where the clock signal to a core of the external application processor is interrupted and/or DC supply voltage to the core of the external application processor is removed or interrupted. The interruption of the clock signal to the core of the external application processor may be controlled by a clock gating circuit and reduces dynamic power dissipation of the core).
Regarding Claim 13. Mortensen discloses avoice activity detection method, comprising:
generating first audio data according to an audio signal from an audio generator circuit (Mortensen, Para 0007, A first aspect of the invention relates to a microphone circuit assembly for an external application processor, comprising: a microphone preamplifier comprising an input terminal for receipt of a microphone signal, an analog-to-digital converter configured for receipt of an output signal of the microphone preamplifier and generation of corresponding microphone signal samples having a first predetermined number of bits at a first predetermined sample rate, a speech feature extractor configured for receipt and processing of predetermined blocks of the microphone signal samples to extract speech feature vectors representing speech features of the microphone signal samples), and storing the first audio data to a first memory (Mortensen, Para 0021, another preferred embodiment of the microphone circuit assembly comprises a circular speech data buffer configured for storage of consecutive speech segments representing predetermined time periods of the microphone signal samples. The circular speech data buffer may reside in a suitable data memory area or segment of the microphone circuit assembly such as a register file or SRAM data memory area);
controlling a processor to execute a first program code in the first memory and to operate in a first mode (Mortensen, Para 0014, According to another preferred embodiment of the microphone circuit assembly the microphone preamplifier and analog-to-digital converter are operative in at least a first power mode and a second power mode);
switching to operating in a second mode by the processor in response to an interrupt signal from the audio generator circuit so as to execute a second program code in a second memory, in order to determine whether the first audio data stored in the first memory includes a human voice signal (Mortensen, para 0014-0015, According to another preferred embodiment of the microphone circuit assembly the microphone preamplifier and analog-to-digital converter are operative in at least a first power mode and a second power mode. The first power mode has a first power consumption and the microphone signal samples are generated at the first predetermined sample rate with a first dynamic range. The second power mode has a second power consumption and the microphone signal samples are generated with a second dynamic range at a second predetermined sample rate. The second dynamic range is larger than the first dynamic range and the second power consumption is larger than the first power consumption. This embodiment allows the microphone circuit assembly to be operated at different microphone signal quality or performance levels with corresponding power consumption levels depending on a system state. The first power mode may be a low-power mode or reduced performance mode of the microphone circuit assembly suitable for wake-up system applications as discussed above. The controller of the microphone circuit assembly may be configured to switch from the first power mode to the second power mode in response to the recognition of the target word or phrase. In a preferred embodiment, the controller is further adapted to initiate transmission of the microphone signal samples through the data communication interface in response to the recognized target word or phrase. Hence, the microphone circuit assembly may be configured to interrupt the transmission of the microphone signal samples in the first power mode to minimize power consumption. The second power mode may be a nominal performance mode in which the microphone signal samples are generated with a larger dynamic range and/or higher sampling rate than in the first power mode/low-power mode albeit at the expense of increased power consumption of the microphone preamplifier and analog-to-digital converter. A low power consumption of the microphone circuit assembly while the associated external application processor and system reside in sleep-mode awaiting the predetermined target word or phrase to wake-up and switch to normal operation represents one distinct advantage of this switchable power mode feature for voice activated system power-up applications), wherein power consumption of the processor operating in the first mode is lower than that in the second mode (Mortensen, Para 0008-0009, This feature allows the external application processor to reside in a power savings mode such as a power-down or sleep-mode without processing of the incoming microphone signal until receipt of the recognition signal… This feature leads to a beneficial reduction of computational load and power consumption of the external application processor); and
when the processor determines that the first audio data includes the human voice signal, controlling the first memory to transfer the first audio data to the second memory, and storing second audio data to the second memory, wherein the processor generates the second audio data according to the audio signal after generating the first audio data (Mortensen, para 0022, The microphone circuit assembly may comprise a floating point converter operatively coupled between an output of the analog-to-digital converter and an input of the speech feature extractor, [i.e., equivalent to the first memory]), the processor further controls the first memory to transfer the first audio data to the second memory, and the audio processing circuit further stores second audio data to the second memory, wherein the audio processing circuit generates the second audio data according to the audio signal after generating the first audio data (Mortensen, para 0021, the microphone circuit assembly comprises a circular speech data buffer configured for storage of consecutive speech segments representing predetermined time periods of the microphone signal samples. The circular speech data buffer may reside in a suitable data memory area or segment of the microphone circuit assembly such as a register file or SRAM data memory area. The size or capacity of the circular speech data buffer varies according to its intended application. In some embodiments, the circular speech data buffer functions only as a temporary storage area for the speech feature extractor allowing blocks of microphone signal samples to be accumulated and temporarily stored before subsequent processing in a block based filter bank algorithm such as a MFCC filter bank. In these embodiments the circular speech data buffer may be sized to hold between 256 and 1024 microphone signal samples. In other embodiments, the circular speech data buffer has capacity to hold relatively large consecutive segments of the microphone signal samples for example microphone signal samples representing a time period larger than one of 500 ms and 1 second. These time periods correspond to 8.000 and 16.000 microphone signal samples, respectively, at a sample rate of 16 kHz. The large storage capacity of the circular speech data buffer is utilized in advantageous embodiment of the invention where the controller is configured to, in response to a recognized target word or target phrase, transmitting a speech segment comprising the recognized target word or phrase from the circular speech data buffer to the external application processor through the data communication interface; According to a preferred embodiment of the Digital Signal Processing System 400, the software programmable DSP 402 comprises a speech recognition application or program routine comprising a set of executable program instructions configured to, in response to receipt of the recognition signal, read the previously discussed selected speech segment transmitted by the microphone circuit assembly 201 through the bi-directional data interface 422; … the programmable DSP where the data communication interface is configured for receipt of microphone signal samples transmitted by the microphone circuit assembly subsequently to issuance of the recognition signal”; “transmitted…audio” as “transferred ..audio”]; Mortensen, para 0040, The present embodiment of the circular speech data buffer 214 comprises a second output 215 which is coupled to the bi-directional data communication interface 222 or communication interface. The communication interface 222 is configured for transmission of certain portions of the digital microphone samples, for example comprising selected segments of stored speech... After the decision circuit 220 has recognized the target word or phrase and notified the application processor through the previously discussed recognition signal INT_DSP, the controller 226 may be adapted to start transmitting generated microphone signal samples immediately after the above-described selected speech segments).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 are rejected under 35 U.S.C. 103 as being unpatentable over Mortensen Pat App No. US 20140257813 A1 (Mortensen) in view Pedersen et al.et al. Pat App No US 20200053460 A1 (Pedersen).
Regarding Claim 4. Mortensen discloses the voice activity detection device according to claim 2.
Mortensen fundamentally discdiscloses wherein after the first memory transfers the first audio data to the second memory, the first memory further releases a storage space previously storing the first audio data from the first memory
wherein after the first memory transfers the first audio data to the second memory, the first memory further releases a storage space previously storing the first audio data from the first memory ( Pedersen, para 0009, The first audio rendering device is configured to maintain a first buffer of received frames of audio data for the first audio channel and to release, at respective first buffer release times, frames of audio data for the first audio channel from said first buffer for rendering ).
Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the method of Pedersen in the method of Mortensen because this would enable introducing buffers at the first and second audio rendering devices and by synchronising, based on communication between the first and second audio rendering device, release times for releasing frames from the buffers, an efficient system for rendering audio content on two devices in a synchronised manner is provided (Pedersen, para 0010).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Mortensen Pat App No. US 20140257813 A1 (Mortensen) in view of Nanda et al. Pat App No. CN 102789305 A (Nanda).
Regarding Claim 5. Mortensen discloses the voice activity detection device according to claim 1.
Mortensen does not specifically disclose wherein the processor further controls the second memory from operating in a third mode to operating in a fourth mode in response to the interrupt signal, and power consumption of the second memory operating in the third mode is lower than that in the fourth mode.
However, Nanda, in the same field of endeavor, discloses wherein the processor further controls the second memory from operating in a third mode to operating in a fourth mode in response to the interrupt signal, and power consumption of the second memory operating in the third mode is lower than that in the fourth mode (Nanda, para 0023, the computing device 102 may be configured in one or more power mode (e.g., time delay according to the working power mode, suspend power mode, ACPI power mode (as hereinbefore described), etc.) lower operation. In these embodiments, the computing device 102 may be configured to receive from a first power mode (e.g., operating power mode) is changed to the second, third or even fourth power mode (e.g., suspend power mode, sleep power mode, an off power mode, etc.). Similarly, computing device 102 can also be configured from a second (or other) power mode to the first power mode or other power mode).
Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the method of Nanda in the method of Mortensen because this would enable several power modes and between these two power supply mode (working on and off), performance characteristics of said plural power modes would compromise these functions to exchange power or reduce the electric consumption (Nanda, para 0002).
Regarding Claim 6. Mortensen in view of Nanda disclose the voice activity detection device according to claim 5.
Furthermore, Nanda teaches:
wherein the second memory is a dynamic random access memory (DRAM), the third mode is a self-refresh mode, and the fourth mode is an active mode (Nanda, para 0004, when the calculating device in standby, sleep or suspension to RAM state, with the device in active or full power mode lower compared with the consumed electric consumption generally less than about 20% of the total power. However, although the electric consumption and the working power mode compared with greatly reduced, while the sleep power mode to electric is constantly supplied and consumed so as to supply or refresh the volatile memory (e.g., RAM) to avoid operating state from the non-volatile memory is erased).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Mortensen Pat App No. US 20140257813 A1 (Mortensen) in view of Chen Pat App No. TW 202027064 A (Chen).
Regarding Claim 7. Mortensen discloses the voice activity detection device according to claim 1.
Mortensen does not specifically disclose wherein when the processor operates in the first mode, the audio processing circuit stores the first audio data to the first memory.
However, Chen, in the same field of endeavor, discloses wherein when the processor operates in the first mode, the audio processing circuit stores the first audio data to the first memory (Chen, 2nd page, 4th para, Some aspects of the present case provide a voice detection method, which includes the following operations: storing the sound data detected from a microphone in the first memory ).
Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the method of Chen in the method of Mortensen because this would enable the second processing circuit to operate in a second power domain, and the power consumption corresponding to the first power domain would be lower than the power consumption corresponding to the second power domain (Chen, 2nd page, 4th para).
Regarding Claim 8. Mortensen discloses the voice activity detection device according to claim 1.
Mortensen does not specifically disclose wherein when the processor operates in the first mode, the audio processing circuit does not store the first audio data to the first memory.
However, Chen, in the same field of endeavor, discloses wherein when the processor operates in the first mode, the audio processing circuit does not store the first audio data to the first memory (Chen, 2nd page, 3rd para some aspects of the present application provide a processing system that operates in a first power domain and includes a first memory, a memory access circuit, and a first processing circuit. The first memory is used for storing a sound data detected by a microphone. The memory access circuit is used for transferring the voice data to a second memory according to a first command to store it as a voice data ).
Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the method of Chen in the method of Mortensen because this would enable the second processing circuit to operate in a second power domain, and the power consumption corresponding to the first power domain would be lower than the power consumption corresponding to the second power domain (Chen, 2nd page, 4th para).
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over Mortensen Pat App No. US 20140257813 A1 (Mortensen) in view of Soulier et al. Pat App No. US 20220038818 A1 (Soulier).
Regarding Claim 9. Mortensen discloses the voice activity detection device according to claim 1, wherein the audio processing circuit comprises:
an analog-to-digital converter (ADC), converting the audio signal into digital data (Mortensen, para 0052, The proprietary floating point format utilized in the MFCC filter bank may advantageously be adapted such that resolution of the mantissa is largely matched to the dynamic range of the microphone signal samples delivered by the analog-to-digital converter).
Mortensen does not specifically disclose an audio encoder-decoder (codec), processing the digital data to generate the first audio data.
However, Soulier, in the same field of endeavor, discloses an audio encoder-decoder (codec), processing the digital data to generate the first audio data (Soulier, para 0028, The decoder may perform an unpacking of the bitstream (i.e., to obtain an unpacked encoded bitstream) in order to retrieve the encoded audio data and the additional encoded data; Soulier, para 0118-0120, The sub-band samples may correspond to several frequency bands (or frequency ranges). The sub-band samples may be understood as a set of quantized spectral components representing a part of the input audio signal. For instance, in the case of SBC codec, the number of frequency bands may be 4 or 8. In parallel with the filter bank analysis, each channel of the input audio signal may be transferred to a perceptual module 302. From the time domain input signal (i.e., CNL1 and CNL2) and/or from the output of the analysis filter bank, an estimate of the actual (time and frequency dependent) masking threshold (i.e., the threshold below which any signal may not be audible) may be computed using rules known from psychoacoustics. This may be called the perceptual model of the perceptual encoding system. The psychoacoustics may be defined as the scientific study of sound perception and audiology (i.e., how humans may perceive various sounds). More specifically, it may be defined as the branch of science which studies the psychological and physiological responses associated with sound (e.g., noise, speech and music). The psychoacoustics may be used for improving the compression by identifying inaudible sounds in the audio signal which may be removed with a masking threshold before generating a bitstream).
Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the method of Nanda in the method of Mortensen because this would enable generating a first encoded bitstream from the first set of spectral components, and forwarding the first encoded bitstream to a second speaker of the audio rendering system over a wireless link (Soulier, Abstract).
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Mortensen Pat App No. US 20140257813 A1 (Mortensen) in view of Park et al. Pat App No. US 20110058214 A1 (Park).
Regarding Claim 12. Mortensen discloses the voice activity detection device according to claim 1.
Mortensen does not specifically disclose wherein a code size of the first program code is smaller than a code size of the second program code.
However, Park, in the same field of endeavor, discloses wherein a code size of the first program code is smaller than a code size of the second program code (Park, para 0046, The program to control the low power mode includes the USB driver. The USB driver includes only a routine which is in charge of processing control end point and a routine which is needed to be woken to return to the normal mode. The program to control the low power mode requires lower capacity compared with the USB program which is stored in the first memory unit 130 ).
Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the method of Park in the method of Mortensen because this would enable a low power mode in which the power supply to most of the modules is shut down or minimized so as to minimize power consumption when a system is inactive, and in order to implement lower standby power, the power supply is shut down to main memory (in general, external dynamic random access memory (DRAM)) (Park, para 0005).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MULUGETA TUJI DUGDA/Examiner, Art Unit 2653
/DOUGLAS GODBOLD/Primary Examiner, Art Unit 2655
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