DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
1. Claims 1-3, 11-13 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chodem et al (USPN 2023/0418479).
Regarding claim 1, Chodem discloses a data processing system (a data processing system shown in figure 1), comprising:
a processor (a controller 101, see par. 0013); and
a storage device (a memory 103, storage medium 102), comprising:
memory (a storage medium 102) for temporarily storing data (see par. 0013);
persistent storage (a flash memory 103) for permanently storing data; and
power protection circuitry (a back-up power circuit shown in figure 2, see par. 0031) adapted to temporarily provide power to the storage device when the data processing system unexpectedly loses power,
the power protection circuitry comprising:
capacitor banks (such as capacitors C1 to C10 shown in figure 2a) for storing the power prior to occurrences of unexpected losses of power, and an isolation mechanism (204) adapted to electrically isolate any capacitor banks of the capacitor banks that suffer capacitor failures (see par. 0033-0034).
Regarding claim 2, Chodem discloses wherein the capacitor banks (C1 to C10) are over provisioned with respect to a quantity of power necessary to complete a shutdown procedure for the storage device (102, 103, see par. 0031).
Regarding claim 3, Chodem discloses wherein the isolation mechanism (204) is adapted to electrically isolate each of the capacitor banks (C1-C10) that has suffered a capacitor failure from other capacitor banks of the capacitor banks that have not suffered any capacitor failures (e.g. see 0034, 0038).
Regarding claim 11, Chodem discloses a storage device (100 shown in figure 1), comprising:
Memory (102) for temporarily storing data;
persistent storage (103) for permanently storing data; and
power protection circuitry (a protection circuit shows details in figure 2b) adapted to temporarily provide power (a back-up power circuit shown in figure 2, see par. 0031) to the storage device (100) when a data processing system hosting the storage device unexpectedly loses power, the power protection circuitry comprising:
capacitor banks (capacitor banks C1-C10) for storing the power prior to occurrences of unexpected losses of power, and an isolation mechanism (204) adapted to electrically isolate any capacitor banks of the capacitor banks that suffer capacitor failures (see par. (see par. 0033-0034).
Regarding claim 12, Chodem discloses wherein the capacitor banks (C1-C10) are over provisioned with respect to a quantity of power necessary to complete a shutdown procedure for the storage device (102, 103, see par. 0031).
Regarding claim 13, Chodem discloses wherein the isolation mechanism (204) is adapted to electrically isolate each of the capacitor banks (C1-C10) that has suffered a capacitor failure from other capacitor banks of the capacitor banks that have not suffered any capacitor failures (e.g. see 0034, 0038).
2. Claims 1-4, 6, 10-14, 20 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Vijayvargiya (USPN 2014/0186818).
Regarding claim 1, Vijayvargiya discloses a data processing system (a data processing system 100 shown in figure 1), comprising:
a processor (a controller 123, see par. 0034); and
a storage device (110, 118), comprising:
memory (118) for temporarily storing data;
persistent storage (110) for permanently storing data (see par. 0031); and
power protection circuitry (a back-up power circuit 134 shown in figure 1, and details in figure 3, see par. 0037, 0043) adapted to temporarily provide power to the storage device when the data processing system unexpectedly loses power,
the power protection circuitry comprising:
capacitor banks (such as capacitors 314a to 314N shown in figure 3) for storing the power prior to occurrences of unexpected losses of power, and an isolation mechanism (310) adapted to electrically isolate any capacitor banks of the capacitor banks that suffer capacitor failures (see par. 0037, 0044, 0050).
Regarding claim 2, Vijayvargiya discloses wherein the capacitor banks (C1 to C10) are over provisioned with respect to a quantity of power necessary to complete a shutdown procedure for the storage device (118, 110, see par. 0055).
Regarding claim 3, Vijayvargiya discloses wherein the isolation mechanism (310) is adapted to electrically isolate each of the capacitor banks (314a-314N) that has suffered a capacitor failure from other capacitor banks of the capacitor banks that have not suffered any capacitor failures (e.g. see 0050).
Regarding claim 4, Vijayvargiya discloses wherein the isolation mechanism (310) comprises diodes (such as each isolation switch 310 includes diodes 352, 354) that that are positioned to isolate output for each of the capacitor banks (see par. 0045, and figure 3).
Regarding claim 6, Vijayvargiya discloses wherein the isolation mechanism comprises transistors (356, 358) that are adapted to selectively electrically float each of the capacitor banks (see par. 0050, and figure 3).
Regarding claims 10, 20, Vijayvargiya discloses wherein the capacitor banks (314a-314N) comprise solid state capacitors (such as the capacitor banks 314a-314N are implemented as tantalum capacitors, see par. 0041) that are subject to the capacitor failures.
Regarding claim 11, Vijayvargiya discloses a storage device (102 shown in figure 1), comprising:
Memory (118) for temporarily storing data (see par. 0032);
persistent storage (110) for permanently storing data (see par. 0031); and
power protection circuitry (a protection circuit 134 shows details in figure 3) adapted to temporarily provide power to the storage device when a data processing system hosting the storage device unexpectedly loses power (see par. 0037, 0043), the power protection circuitry comprising:
capacitor banks (capacitor banks 314a-314N) for storing the power prior to occurrences of unexpected losses of power, and an isolation mechanism (310) adapted to electrically isolate any capacitor banks of the capacitor banks that suffer capacitor failures (see par. 0037, 0044, 0050).
Regarding claim 12, Vijayvargiya discloses wherein the capacitor banks (C1 to C10) are over provisioned with respect to a quantity of power necessary to complete a shutdown procedure for the storage device (118, 110, see par. 0055).
Regarding claim 13, Vijayvargiya discloses wherein the isolation mechanism (310) is adapted to electrically isolate each of the capacitor banks (314a-314N) that has suffered a capacitor failure from other capacitor banks of the capacitor banks that have not suffered any capacitor failures (e.g. see 0050).
Regarding claim 14, Vijayvargiya discloses wherein the isolation mechanism (310) comprises diodes (such as each isolation switch 310 includes diodes 352, 354) that that are positioned to isolate output for each of the capacitor banks (see par. 0045, and figure 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 5, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Vijayvargiya (USPN 2014/0186818) in view of Zupanc et al (USPN 2019/0041938).
Regarding claims 5, 15, Vijayvargiya discloses all limitations of claims 1, 3, 4, 11, 13, 14 as discussed above, but does not explicitly disclose a current limiter as claimed.
Zupanc discloses a fault protection for a power failure comprises an isolation circuit (220)(see figure 2) comprises a current limiter (224) for that limit current draw by a capacitor bank (230) (see par. 0032).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the isolation mechanism of Vijayvargiya to incorporate a current limiter as disclosed by Zupanc in order to limit a current flow during an event of failure of the capacitor bank.
4. Claims 6-9, 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chodem et al (USPN 2023/04/18479) in view of Vijayvargiya (USPN 2014/0186818).
Regarding claims 6, 7, 16, 17, Chodem discloses wherein the isolation mechanism comprises switches (208) that are adapted to selectively electrically float each of the capacitor banks (see par. 0031, and figure 2b), wherein the isolation mechanism comprises a local controller (such as a local controller includes circuits 212, 216) adapted to use the switches (208) to selectively electrically float each of the capacitor banks (C1-C10) based on a state reading of the capacitor banks (e.g. see par. 0034).
Chodem does not explicitly disclose the isolation mechanism includes transistors as claimed.
Vijayvargiya discloses a circuit failure protection device (see figure 3) comprises an isolation mechanism includes transistors (310).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the isolation mechanism of Chodem to incorporate transistors as disclosed by Vijayvargiya in order to provide a fast switching speed, lower conduction loss. Thus, improving a switching performance.
Regarding claims 8, 18, Chodem discloses wherein the local controller (the 212, 216 shown in figure 2b) is adapted to: monitor a charge level of the capacitor banks (such as charge levels of the capacitor banks C1-C10 monitored by circuits 212, 216); and in an instance of the charge level being below a threshold: perform a diagnostic procedure to identify any of the capacitor banks that have suffered a capacitor failure (see par. 0032, 0034).
Regarding claims 9, 19, Chodem discloses wherein the local controller (212) is further adapted to: send control signals to the switches (208) corresponding to the any of the capacitor banks that have suffered a capacitor failure to float the any of the capacitor banks that have suffered a capacitor failure, wherein the controls signal electrically isolate the switches corresponding to the any of the capacitor banks that have suffered a capacitor failure from a ground (ground nodes 214) for the storage device to eliminate voltage potentials across the switches (208) corresponding to the any of the capacitor banks that have suffered a capacitor failure (see par. 0034, 0037, 0038).
Chodem does not explicitly disclose the isolation mechanism includes transistors as claimed.
Vijayvargiya discloses a circuit failure protection device (see figure 3) comprises an isolation mechanism includes transistors (310).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the isolation mechanism of Chodem to incorporate transistors as disclosed by Vijayvargiya in order to provide a fast switching speed, lower conduction loss. Thus, improving a switching performance.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY NGUYEN whose telephone number is (571)272-2054. The examiner can normally be reached M-F 8:00AM-4:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-271-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANNY NGUYEN/ Primary Examiner, Art Unit 2838