Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 6, 7, 9, 10, 12-16, 18-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al. (US 20190096791 A1) hereafter referred to as Jeng in view of Wu et al. (US 20240071855 A1) hereafter referred to as Wu. Gu et al. (US 20190260109 A1) hereafter referred to as Gu is provided as evidence of ordinary skill in the art in claim 3.
In regard to claim 1 Jeng teaches [see “The design concepts of the integrated fan-out package 30 of FIG. 6 and the integrated fan-out package 40 of FIG. 7 can be combined, so as to provide an integrated fan-out package 50 which can dissipate heat more effectively, as shown in FIG. 8”] a semiconductor package comprising:
a first redistribution structure [“the redistribution layer structure 102 includes a plurality of redistribution layers 103 embedded by a plurality of polymer layers 104”] comprising a plurality of first redistribution layers;
a second redistribution structure [“Referring to FIG. 1D, a redistribution layer structure 106 is formed over the first semiconductor chip 100. In some embodiments, the redistribution layer structure 106 is formed to thermally connect to the heat dissipation layer 100d of the first semiconductor chip 100”] above the first redistribution structure;
a first semiconductor chip [“the first semiconductor chip 100 includes a substrate 100a, one or more connectors 100b, one or more bumps 100c and a heat dissipation layer 100d”] on the first redistribution structure and arranged between the first redistribution structure and the second redistribution structure;
a conductive block directly [“at least one thermal through integrated fan-out via TTIV”] contacting the first redistribution structure and the second redistribution structure and extending [the Examiner notes that see Fig. 8 the TTIV have a finite width horizontally, contacting 106 at the top and 102 at the bottom, thus under broadest reasonable interpretation it is “extending” ] in a horizontal direction between the first redistribution structure and the second redistribution structure; and
a plurality of conductive posts [ see the TIV in Fig. 8, “the first semiconductor chip 100, the first semiconductor chip 100, the through integrated fan-out vias TIV and the at least one thermal through integrated fan-out via TTIV are encapsulated with an encapsulation layer E”] around the first semiconductor chip and the conductive block, the plurality of conductive posts extending in a [see Fig. 8] vertical direction and directly contacting [see Fig. 8] the first redistribution structure and the second redistribution structure
but does not state the second redistribution structure comprising a plurality of second redistribution layers.
However see Fig. 8 see that “In some embodiments, the package 200 further includes a conductive structure 202, a plurality of bumps 206 and a plurality of thermal bumps TB1 and TB2” “In some embodiments, the conductive structure 202 is a front-side redistribution layer structure at a front side of the second semiconductor chip 201. In alternative embodiments, the conductive structure 202 is a backside redistribution layer structure at a back side of the second semiconductor chip 201”.
See Wu Fig. 6, Fig. 9 “back-side redistribution circuit structure 215 formed over the de-bonding layer DB may include a plurality of inter-dielectric layers 215a and a plurality of redistribution conductive layers 215b stacked alternately” “semiconductor substrate 110 may be a silicon substrate including active components (e.g., transistors or the like) and passive components (e.g., resistors, capacitors, inductors, or the like)” “the front-side redistribution circuit structure 220 includes a plurality of inter-dielectric layers 222 and a plurality of redistribution conductive layers 224 stacked alternately” “Referring to FIG. 14, an electronic device (i.e., a package) 300 including conductive terminals 260 formed thereon is then provided” “electronic device 300 may be or include a memory device, such as a dynamic random access memory (DRAM) device ...”. See that in Fig. 14 the memory 300 has “conductive terminals 260 may be or include conductive bumps (e.g., copper bumps, solder bumps or the like)”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Jeng to include the second redistribution structure comprising a plurality of second redistribution layers.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to increase the routing ability of the redistribution layer structure 106 to allow attaching components such as memory.
In regard to claim 2 Jeng and Wu as combined does not specifically teach wherein, in a plan view, each of the plurality of conductive posts has a dot shape and the conductive block has a planar shape.
However see “the thermal vias TV are circular, oval, square, rectangular, polygonal or a combination thereof”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Jeng to include wherein, in a plan view, each of the plurality of conductive posts has a dot shape and the conductive block has a planar shape.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that the thermals vias conduct heat so a larger via allows more heat to escape however non-thermal vias connect to interconnects which cannot be so large as to cause parasitic capacitances to other conductive layers.
In regard to claim 3 Jeng and Wu as combined does not teach wherein: the plurality of first redistribution layers comprises a first adjacent redistribution layer positioned closest to the first semiconductor chip among the plurality of first redistribution layers; the first adjacent redistribution layer comprises a first signal pattern; and the conductive block overlaps the first signal pattern in the vertical direction.
However see Jeng Fig. 8 see the “bumps 108 are placed over and bonded to the connecting pads of the redistribution layer structure 102” see evidence of Gu paragraph 0048 “Moreover, one of ordinary skill in the art will recognize that the one or more integrated circuits 202 can comprise respective flip chip pads, ground pads, DC power supply pads, input/output pads, and/or control signal pads”, thus some of the 108 carry input/output signal.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Jeng to include wherein: the plurality of first redistribution layers comprises a first adjacent redistribution layer positioned closest to the first semiconductor chip among the plurality of first redistribution layers; the first adjacent redistribution layer comprises a first signal pattern; and the conductive block overlaps the first signal pattern in the vertical direction.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that each layer in 102 is electrically isolated from the layer above it and so for design flexibility of the chip and the substrate to which bumps 108 connect, any 108 can be used for signal.
In regard to claim 4 Jeng and Wu as combined does not specifically teach wherein, in a plan view, the conductive block has a line shape.
However see “the thermal vias TV are circular, oval, square, rectangular, polygonal or a combination thereof”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Jeng to include wherein, in a plan view, the conductive block has a line shape.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that the thermals vias conduct heat so a larger via allows more heat to escape.
In regard to claim 5 Jeng and Wu as combined teaches wherein the conductive block is electrically insulated [see Jeng Fig. 8 each layer in 102 is electrically isolated from the layer above it] from the first signal pattern.
In regard to claim 8 Jeng and Wu as combined does not specifically teach wherein: the plurality of second redistribution layers comprises a second adjacent redistribution layer positioned closest to the first semiconductor chip among the plurality of second redistribution layers; the second adjacent redistribution layer comprises a second signal pattern; and the conductive block overlaps the second signal pattern in the vertical direction.
However see Jeng Fig. 8 see the “bumps 108 are placed over and bonded to the connecting pads of the redistribution layer structure 102” see evidence of Gu paragraph 0048 “Moreover, one of ordinary skill in the art will recognize that the one or more integrated circuits 202 can comprise respective flip chip pads, ground pads, DC power supply pads, input/output pads, and/or control signal pads”, thus some of the 108 carry input/output signal.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Jeng to include wherein: the plurality of second redistribution layers comprises a second adjacent redistribution layer positioned closest to the first semiconductor chip among the plurality of second redistribution layers; the second adjacent redistribution layer comprises a second signal pattern; and the conductive block overlaps the second signal pattern in the vertical direction.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that each layer in 102 is electrically isolated from the layer above it and so for design flexibility of the chip and the substrate to which bumps 108 connect, any 108 can be used for signal.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tain et al. (US 20090294947 A1) hereafter referred to as Tain in view of Jeng et al. (US 20190096791 A1) hereafter referred to as Jeng. Gu et al. (US 20190260109 A1) hereafter referred to as Gu is provided as evidence of ordinary skill in the art.
In regard to claim 11 Tain teaches [see “FIG. 5 is a schematic cross-sectional view of a chip package structure having stacked chip package units”, see also flip-chip Figs. 3A-3B] a semiconductor package comprising:
a first redistribution structure [see bottommost 114 “In the present embodiment, the connecting circuit 114 is, for example, an interconnect located in the substrate 102, while in other exemplary embodiments the connecting circuit 114 can also be located on the surface of the substrate 102” “signal solder balls 142 are connected to the signal vias 116 through the signal lines 134, such that signals in the chip package structure 100' can be transmitted outwardly, or external signals can be received”] comprising a first redistribution pattern comprising a first signal pattern;
a second redistribution structure above [see the middle 114] the first redistribution structure, the second redistribution structure comprising a second redistribution pattern comprising and a second signal pattern;
a first semiconductor chip [see bottommost “chip 104”] on the first redistribution structure and arranged between [see FIG. 5] the first redistribution structure and the second redistribution structure;
a second semiconductor chip [see middle “chip 104”] on the second redistribution structure and comprising [see that under broadest reasonable interpretation all the chips 104 are heating areas because of inherent Joule heating ] a heating area;
conductive block [“thermal conductive layer 106 is disposed over the substrate 102, connected to the thermal conductive vias 112, and located above the chip disposing region 118” “in other exemplary embodiments, the thermal conductive layer 106 can also be merely located over the top surface of the substrate 102” see that 106 is conductive “Note that insulation layers 107 are required to be disposed between the signal contacts 108a and the thermal conductive layer 106, so as to prevent the signal contacts 108a from being electrically connected to the thermal conductive layer 106”] each having a wall shape extending in a horizontal direction between [see FIG. 5] the first redistribution structure and the second redistribution structure, the conductive block directly contacting the first redistribution structure and the second redistribution structure;
a plurality of conductive posts [i.e. 108a see Fig. 5 “signal contacts 108a are connected to the signal vias 116, and the insulation layers 107 are disposed between the signal contacts 108a and the thermal conductive layer 106”] around the first semiconductor chip, the plurality of conductive posts directly contacting [“the signal vias 116 of the upper chip package unit 500 are connected to the signal contacts 108a of the lower chip package unit 500”] the first redistribution structure and the second redistribution structure, the plurality of conductive posts each having a pillar [see Fig. 5 “signal contacts 108a are connected to the signal vias 116, and the insulation layers 107 are disposed between the signal contacts 108a and the thermal conductive layer 106”] shape extending in a vertical direction; and
an encapsulation material [“the molding compound 110 is filled into the space between the substrate 102 and the thermal conductive layer 106 through openings 10, so as to encapsulate the chip 104”] between the first redistribution structure and the second redistribution structure, the encapsulation material surrounding the first semiconductor chip
but does not mention a first ground pattern, a first power pattern and a second ground pattern, a second power pattern and does not state that conductive block is “a plurality of” and that the plurality of conductive posts are around the conductive blocks and that the encapsulation material surrounding the plurality of conductive blocks, and the plurality of conductive posts.
However see “In the present embodiment, the connecting circuit 114 is, for example, an interconnect located in the substrate 102, while in other exemplary embodiments the connecting circuit 114 can also be located on the surface of the substrate 102” and also see that “the thermal conductive layer 106 is connected to the thermal conductive vias 112” i.e. 112 are also part of the conductive block.
So the Fig. 5 does not show the case when the connecting circuit 114 is located on the surface of the substrate 102.
With regard to power and ground, the Examiner notes that a person of ordinary skill in the art knows that chips use power to function, see as evidence Gu paragraph 0048 “Moreover, one of ordinary skill in the art will recognize that the one or more integrated circuits 202 can comprise respective flip chip pads, ground pads, DC power supply pads, input/output pads, and/or control signal pads”.
See Jeng teaches “The design concepts of the integrated fan-out package 30 of FIG. 6 and the integrated fan-out package 40 of FIG. 7 can be combined, so as to provide an integrated fan-out package 50 which can dissipate heat more effectively, as shown in FIG. 8” “at least one thermal through integrated fan-out via TTIV” see the “a plurality of through integrated fan-out vias TIV are formed over the redistribution layer structure 102” see the TIV are around the TTIV see “the encapsulation layer E is formed over the carrier C to encapsulate or surround the sidewalls of the through integrated fan-out vias TIV, the sidewall of the at least one thermal through integrated fan-out via TTIV and the sidewall and top of the first semiconductor chip 100”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tain to include a first ground pattern, a first power pattern and a second ground pattern, a second power pattern and does not state that conductive block is “a plurality of” and that the plurality of conductive posts are around the conductive blocks and that the encapsulation material surrounding the plurality of conductive blocks, and the plurality of conductive posts.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that a person of ordinary skill in the art knows that chips use power to function and that for the case when the Tain connecting circuit 114 is located on the surface of the substrate 102, the encapsulation is useful to hold and protect and isolate the components and that plurality of blocks help channel the heat better and that distributing the placement is ease of design and manufacture.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tain et al. (US 20090294947 A1) hereafter referred to as Tain in view of Jeng et al. (US 20190096791 A1) hereafter referred to as Jeng. Gu et al. (US 20190260109 A1) hereafter referred to as Gu is provided as evidence of ordinary skill in the art.
In regard to claim 17 Tain teaches [see “FIG. 5 is a schematic cross-sectional view of a chip package structure having stacked chip package units”, see also flip-chip Figs. 3A-3B] a semiconductor package comprising:
a first redistribution structure [see bottommost 114 “In the present embodiment, the connecting circuit 114 is, for example, an interconnect located in the substrate 102, while in other exemplary embodiments the connecting circuit 114 can also be located on the surface of the substrate 102” “signal solder balls 142 are connected to the signal vias 116 through the signal lines 134, such that signals in the chip package structure 100' can be transmitted outwardly, or external signals can be received”] comprising a first redistribution pattern comprising a first signal pattern;
a second redistribution structure [see the middle 114] above the first redistribution structure, the second redistribution structure comprising a second redistribution pattern comprising a second signal pattern;
a first semiconductor chip [see bottommost “chip 104”] on the first redistribution structure and arranged between [see FIG. 5] the first redistribution structure and the second redistribution structure;
a second semiconductor chip [see middle “chip 104”] on the second redistribution structure and comprising [see that under broadest reasonable interpretation all the chips 104 are heating areas because of inherent Joule heating ] a heating area;
a conductive block [“thermal conductive layer 106 is disposed over the substrate 102, connected to the thermal conductive vias 112, and located above the chip disposing region 118” “in other exemplary embodiments, the thermal conductive layer 106 can also be merely located over the top surface of the substrate 102” see that 106 is conductive “Note that insulation layers 107 are required to be disposed between the signal contacts 108a and the thermal conductive layer 106, so as to prevent the signal contacts 108a from being electrically connected to the thermal conductive layer 106”] extending in a horizontal direction between [see FIG. 5] the first redistribution structure and the second redistribution structure, the plurality of conductive blocks directly contacting [see FIG. 5] the first redistribution structure and the second redistribution structure, the plurality of conductive blocks comprising a heat dissipation [“in the exemplary embodiment depicted in FIG. 1B, the thermal conductive layer 106 contacts the active surface 104a of the chip 104, thus further improving heat dissipating efficacy”] block, a shielding block [see that 106 is on top and sides of each substrate 102 thus acting as a heat shield]; and
a plurality of conductive posts [i.e. 108a see Fig. 5 “signal contacts 108a are connected to the signal vias 116, and the insulation layers 107 are disposed between the signal contacts 108a and the thermal conductive layer 106”] around the first semiconductor chip, the plurality of conductive posts extending in a vertical direction and directly contacting the first redistribution structure and the second redistribution structure
but does not mention a first ground pattern, a first power pattern, and a second ground pattern, a second power pattern, and does not state that the conductive block is a plurality of and that the plurality of conductive blocks comprising a power block, and that the plurality of conductive posts is around the plurality of conductive blocks.
However see “In the present embodiment, the connecting circuit 114 is, for example, an interconnect located in the substrate 102, while in other exemplary embodiments the connecting circuit 114 can also be located on the surface of the substrate 102” and also see that “the thermal conductive layer 106 is connected to the thermal conductive vias 112” i.e. 112 are also part of the conductive block, see “A heat sink 128 is disposed in the opening 126 and connected to the back surface 104b of the chip 104, which is conducive to an increase in heat dissipating capacity of the chip package structure 100''”, the Examiner notes that in a chip, the substrate is ground for good chip operation.
So the Fig. 5 does not show the case when the connecting circuit 114 is located on the surface of the substrate 102.
With regard to power and ground, the Examiner notes that a person of ordinary skill in the art knows that chips use power to function, see as evidence Gu paragraph 0048 “Moreover, one of ordinary skill in the art will recognize that the one or more integrated circuits 202 can comprise respective flip chip pads, ground pads, DC power supply pads, input/output pads, and/or control signal pads”.
See Jeng teaches “The design concepts of the integrated fan-out package 30 of FIG. 6 and the integrated fan-out package 40 of FIG. 7 can be combined, so as to provide an integrated fan-out package 50 which can dissipate heat more effectively, as shown in FIG. 8” “at least one thermal through integrated fan-out via TTIV” see the “a plurality of through integrated fan-out vias TIV are formed over the redistribution layer structure 102” see the TIV are around the TTIV see “the encapsulation layer E is formed over the carrier C to encapsulate or surround the sidewalls of the through integrated fan-out vias TIV, the sidewall of the at least one thermal through integrated fan-out via TTIV and the sidewall and top of the first semiconductor chip 100”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tain to include a first ground pattern, a first power pattern, and a second ground pattern, a second power pattern, and does not state that the conductive block is a plurality of and that the plurality of conductive blocks comprising a power block, and that the plurality of conductive posts is around the plurality of conductive blocks.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that a person of ordinary skill in the art knows that chips use power to function and that 106 is conductive and touching the back of the chip substrate thus it is ground for good chip operation and that for the case when the Tain connecting circuit 114 is located on the surface of the substrate 102, the encapsulation is useful to hold and protect and isolate the components and that plurality of blocks help channel the heat better and that distributing the placement is ease of design and manufacture.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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