DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 04/30/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on 04/30/24. The drawings are acceptable.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17-20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 as currently presented, does not fall within at least one of the four categories of patent eligible subject matter because “computer readable medium” of claim 17 encompasses signals per se. The specification offers an assertion in par [0048] “A computer readable storage medium, as that term is used in the present disclosure, is not to be construed as storage in the form of transitory signals per se, such as radio waves …”. Therefore the broadest reasonable interpretation of the “computer readable medium” is to be “non-transitory computer readable medium”. As understood in light of the specification, the broadest reasonable interpretation of claim 17 encompasses non-transitory signals.
The Examiner suggests that the Applicant amend the limitation to add "non-transitory" in order to properly render the claim in statutory form in view of its broadest reasonable interpretation in light of the originally filed specification, in order to be consistent with the originally filed specification. For the purpose of examination, the computer readable storage medium is considered to be a non-transitory computer readable storage medium.
Claims 18-20 are rejected for their dependency on rejected claim 17 above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jain et al. (US 20250111121 A1), hereinafter Jain.
Regarding claims 1 and 9, Jain discloses a system/method for on-die control for active interposer voltage regulation, comprising: an active interposer (par [0018]; fig 1, silicon interposer on active interposer die 120A-120C) including voltage regulation circuitry (par [0025] “active interposer dies 120A-120C includes signal interconnects, embedded passive components, such as inductors and decoupling capacitors, voltage regulators, and active devices (or transistors)” , i.e. circuitry), wherein the voltage regulation circuitry includes a switch (par [0025] “active devices (or transistors)”, i.e. switch; see fig 1, 120A) to receive an input voltage (par [0025] the voltage regulators and transistors implies input voltage; par [0031] “operating power supply voltage … of the active interposer dies 120A…”; examiner interprets the operating power supply to the active interposer as an input voltage); and a chip die connected to the active interposer (fig 1, each active interposer die 120A-120C including silicone interposer is connected to computation dies 150A-150I), wherein the chip die includes voltage regulation control circuitry to control the voltage regulation circuitry (par [0026] “circuitry”; par [0034] “hardware, such as circuitry”), including causing the switch to couple the input voltage to one or more passive components of the voltage regulation circuitry (par [0025] “embedded passive components, such as inductors and decoupling capacitors, voltage regulators, and active devices (or transistors)”; par [0035] “each of the active interposer dies 120A-120C includes active devices used to implement the functionality of various components”), wherein the voltage regulation circuitry regulates the input voltage to generate a regulated output voltage that is output to the chip die (par [0022] signals and electrical interface to computation dies 150A-150I).
Regarding claim 2 and 10, Jain discloses the system/method of claim 1, wherein the active interposer is positioned on a module (par [0021] silicone active interposers are positioned on the active imposer dies which can be considered each as individual modules. Alternatively the layers can be considered a module. The instant application failed to disclose the function or description of the module, therefore examiner considers each of the examples to suffice.), and the module is positioned on a board (fig 1, each active interposer die is positioned on package substrate 110, i.e. “board”).
Regarding claim 3 and 11, Jain discloses the system/method of claim 2, wherein the input voltage received by the switch is provided from the board through the module to the active interposer (par [0019] “The package substrate 110 … provides an electrical interface; par [0020] “vertical through silicon vias (TSVs)” provides the electrical connection to the die; par [0022] “the active interposer dies 120A-120C also use TSVs and through silicon buses”; the electrical input to the active interposer is received through TSVs from the package substrate 110).
Regarding claim 4 and 12, Jain discloses the system/method of claim 1 wherein the chip die is a processor chip die that includes one or more processor cores (par [0023] “Each of the computation dies 150A-150I include circuitry for processing data such as one or more processor cores”).
Regarding claim 5 and 13, Jain discloses the system/method of claim 1, wherein the one or more passive components include one or more inductors or one or more capacitors (par [0025] “embedded passive components, such as inductors and decoupling capacitors”).
Regarding claim 6 and 14, Jain discloses the system/method of claim 1, wherein the chip die further includes chip power management circuitry (par [0034] “circuitry of the power manager 124”; “the power manager 124 is shown being located in the active interposer die 120B, in other implementations, the power manager 124 is located elsewhere”; examiner interprets from the disclosure that the power manager and its circuitry could be implemented on the computing chip i.e. “chip die”) communicatively coupled to the voltage regulation control circuitry and other circuitry within the chip die (par [0034] power manager 124 is coupled to transfer communications to control circuitry).
Regarding claim 7 and 15, Jain discloses the system/method of claim 6, wherein the voltage regulation control circuitry is controlled by the chip power management circuitry to accomplish one or more power management functions (par [0034] power manager 124 assigns a target operating clock frequency to active interposer dies).
Regarding claim 8 and 16, Jain discloses the system/method of claim 1, wherein feature size of the voltage regulation control circuitry is smaller than feature size of the voltage regulation circuitry (fig 1, control circuitry in computation dies 150A-150I appear to be smaller in size than the active imposer dies active devices 122A-C).
Regarding claim 17, Jain discloses a computer program product comprising a computer readable storage medium (par [0066]), wherein the computer readable storage medium comprises computer program instructions that, when executed: control (par [0066] “the program instructions that implement the methods and/or mechanisms are conveyed or stored on a computer readable medium” ), by voltage regulation control circuitry in a chip die connected to an active interposer, voltage regulation circuitry in the active interposer, including causing a switch of the voltage regulation circuitry to couple an input voltage received by the switch to one or more passive components of the voltage regulation circuitry in the active interposer; and cause the voltage regulation circuitry to regulate the input voltage to generate a regulated output voltage that is output to the chip die (see claim 1 rejection).
Claims 18-20 are the computer program product of claims 2-4 and 10-12 and are rejected for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Choi et al. (US 20180190635 A1) - power management integrated circuit device
Guatala et al. (US 20190044515 A1) - integrated circuit device having separate dies for programmable logic fabric and circuitry
Elsherbini et al. (US 11462463 B2) - multi-die IC package
Sato et al. (US 20230099856 A1) - integrated circuit package module
Dabral et al. (US 20240103238 A1) - system in package structure
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren A Shaw whose telephone number is (571)272-3074. The examiner can normally be reached Mon-Fri 7-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838