Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-22 are pending in this application. Claims 19-20 are canceled. Claims 1, 9, and 17 are amended. Claims 21-22 are new.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 04/30/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on 04/30/24. The drawings are acceptable.
Response to Amendment
The Amendments, filed on 06/29/2026, have been received and made of record. In response to the most recent Office Action, dated 03/27/2026, claim 17 was amended to overcome the 35 U.S.C. 112(b) rejection, accordingly the rejection is withdrawn.
Response to Arguments
Applicant’s amendments, filed on 06/29/2026, have been entered and fully considered. In light of the amendments and new limitations to the claims, the 35 U.S.C. 102(a)(2) rejections have been withdrawn. However, upon further consideration, new grounds of rejections have been made, and applicant's arguments are rendered moot.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-16 and 21-22 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Dabral et al. (US 20240103238 A1).
Regarding claims 1 and 9, Dabral discloses a system/method for on-die control for active interposer voltage regulation (figs 1 and 4A, multi-chip module MCM 100 including a 3D system 110), comprising: an active interposer (par [0030] “mid-layer interposer … include passives such as trench capacitors, or metal-insulator-metal (MIM) capacitors, magnetic elements (inductors, coupled inductors, etc.), or even include active devices”; fig 1 and 4A, mid layer interposer 112) including voltage regulation circuitry (par [0040] “The mid-layer interposer 112 may additionally include a plurality of devices 113, including passive devices … or even active devices such as transistors”; fig 4A, devices 113), wherein the voltage regulation circuitry includes a switch (par [0040] “active devices such as transistors”, transistors are switches; see fig 4A, devices 113 in interposer 112) to receive an input voltage (par [0055] “landing pads 117 can be for low power (Vss) and high power (Vdd) connection”; see fig 4A, landing pads 117 at top of interposer 112 to receive input power for active transistors); and a chip die connected to the active interposer (fig 1 and 4A, first package level 120 and second package level 140 include chip dies i.e. 124, 126, 128 ,122, 142, 144, 146 connected to interposer 112; instant application par [0042] “Although a single chip die 204 is shown in the illustrated example, other examples may include multiple chip dies”), wherein the chip die includes voltage regulation control circuitry to control the voltage regulation circuitry (par [0028] “moderate power die 124 for example, may include a control circuit including various switches to close or open high voltage and low voltage channels from the voltage regulator 104), including causing the switch to couple the input voltage to one or more passive components of the voltage regulation circuitry, wherein the voltage regulation circuitry regulates the input voltage to generate a regulated output voltage that is output to the chip die (par [0029] “passive devices such as capacitors connected to the high voltage and low voltage channels in order to control the voltage output to circuit loads of the various components, including the high power dies 142, 144 or other dies”), wherein the voltage regulation control circuitry is separate from the active interposer (figs 1 and 4A, interposer 112 is separate from control circuitry in dies 124, 126, 128 ,122, 142, 144, 146).
Regarding claim 2 and 10, Dabral discloses the system/method of claim 1, wherein the active interposer is positioned on a module (fig 1 and 4A, interposer 112 is on multi-chip module 100), and the module is positioned on a board (fig 1 and 4A, circuit board 102; par [0028] “the 3D system 110 can be mounted onto a circuit board 102 of the multi-chip module 100”).
Regarding claim 3 and 11, Dabral discloses the system/method of claim 2, wherein the input voltage received by the switch is provided from the board through the module to the active interposer (fig 1, see power rails 106 on mcm board 102; par [0050] “The mid-layer interposers 112 include electrical routing, as well as passive device and/or active devices”; par [0032] “facilitate other crucial functions including but not limited to circuit board power distribution to the 3D system”; par [0034] “Vias may be additionally provided through the bottom components to provide power supply”).
Regarding claim 4 and 12, Dabral discloses the system/method of claim 1 wherein the chip die is a processor chip die that includes one or more processor cores (par [0027] “the second package level 140 can include high speed input/output (HSIO) die 146, and one or more high power dies 142, 144 such as a graphics processing unit (GPU), central processing unit (CPU), artificial intelligence (AI), machine learning logic, radio-frequency (RF) baseband processor, radio-frequency (RF) antenna, signal processors, power management integrated circuit (PMIC), logic, memory, photonics, biochips, silicon interconnect and any combinations thereof”).
Regarding claim 5 and 13, Dabral discloses the system/method of claim 1, wherein the one or more passive components include one or more inductors or one or more capacitors (par [0029] “mid-layer interposer 112 in accordance with embodiments may be passive, and may include an array of passive devices such as capacitors”).
Regarding claim 6 and 14, Dabral discloses the system/method of claim 1, wherein the chip die further includes chip power management circuitry (par [0029] “much of the power management for the dies can be integrated into the 3D system 110, and directly underneath the high power dies 142, 144”; par [0027] power management integrated circuit (PMIC) included in the first package level 120; examiner interprets from the disclosure that the power management circuitry is included in the first package level 120) communicatively coupled to the voltage regulation control circuitry and other circuitry within the chip die (par [0039] “Landing pads 186 can by metal-metal bonded with landing pads 117 and through vias 118 of the mid-layer interposer 112. The metal wiring layers 182 of the silicon interconnect 122 may form die-to-die wiring 192 for interconnection between multiple dies. The complete die-to-die routing path may pass through a portion of the set of through vias 118 extending through the mid-layer interposer, and be connected with die-to-die wiring 192).
Regarding claim 7 and 15, Dabral discloses the system/method of claim 6, wherein the voltage regulation control circuitry is controlled by the chip power management circuitry to accomplish one or more power management functions (par [0027] “PMIC”; par [0034] “voltage regulation can be largely integrated within the 3DIC”; PMIC is a known specialized chip that integrates voltage regulation control circuitry).
Regarding claim 8 and 16, Dabral discloses the system/method of claim 1, wherein feature size of the voltage regulation control circuitry is smaller than feature size of the voltage regulation circuitry (par [0031] “embodiments facilitate die partitioning such that process nodes can be optimized for different intellectual property (IP) blocks”; par [0034] “The components can be different technologies (IP blocks) and formed with different process nodes (e.g. transistor size, etc.)”; examiner interprets explicit statement that components can be formed with different process nodes (e.g., transistor sizes) means the patent supports mixing and matching different manufacturing technologies. In advanced multi-chip modules MCM, voltage regulation circuitry VR/power stages involves power transistors (like MOSFETs) that require larger process nodes (larger feature sizes) to manage high currents and voltages reliably. Voltage regulation control circuitry (logic/IVR) handles digital and low-power analog control, which can be manufactured using a more advanced, significantly smaller process size/node to save area and power).
Regarding claim 21, Dabral discloses the method of claim 1, wherein the switch and the one or more passive components are fabricated in a technology node that is older than a technology node of the chip die (examiner interprets “older technology node” to mean larger transistor sizes and larger physical feature sizes; par [0031] “embodiments facilitate die partitioning such that process nodes can be optimized for different intellectual property (IP) blocks”; par [0034] “The components can be different technologies (IP blocks) and formed with different process nodes (e.g. transistor size, etc.)”; examiner interprets explicit statement that components can be formed with different process nodes (e.g., transistor sizes) means the patent supports mixing and matching different manufacturing technologies by including passive components in an older larger nm node and utilizing newer technology for digital logic components; par [0022] “process node optimization”)
Regarding claim 22, Dabral discloses the method of claim 1, wherein the voltage regulation control circuitry includes low voltage devices and high voltage devices implemented on the chip die (par [0028] “high voltage and low voltage channels from the voltage regulator”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Dabral et al. (US 20240103238 A1) as applied to claim1 and 9 above, and further in view of Loh et al. (US 20230197619 A1) hereinafter Loh.
Regarding claims 17, Dabral discloses control by voltage regulation control circuitry in a chip die connected to an active interposer, voltage regulation circuitry in the active interposer, including causing a switch of the voltage regulation circuitry to couple an input voltage received by the switch to one or more passive components of the voltage regulation circuitry in the active interposer; and cause the voltage regulation circuitry to regulate the input voltage to generate a regulated output voltage that is output to the chip die, wherein the voltage regulation control circuitry is separate from the active interposer (see claim 1 rejection).
Dabral fails to disclose a computer program product comprising a computer readable storage medium, wherein the computer readable storage medium comprises computer program instructions that, when executed: control voltage regulation control circuitry.
Loh discloses a three-dimensional 3D stack of integrated circuit IC dies with interposer and conventional computer program instructions and memory. Loh discloses disclose a computer program product comprising a computer readable storage medium, wherein the computer readable storage medium comprises computer program instructions that, when executed: control voltage regulation control circuitry (par [0037-0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Dabral and incorporate the use of computer program instructions as taught by Loh. The advantage of this design is implementing instructions to execute control of the voltage regulation.
Regarding claims 18, Dabral and Loh disclose the computer program product of claim 17, wherein the active interposer is positioned on a module, and the module is positioned on a board (Dabral fig 1 and 4A, interposer 112 is on multi-chip module 100 on circuit board 102; par [0028] “the 3D system 110 can be mounted onto a circuit board 102 of the multi-chip module 100”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Choi et al. (US 20180190635 A1) - power management integrated circuit device
Guatala et al. (US 20190044515 A1) - integrated circuit device having separate dies for programmable logic fabric and circuitry
Elsherbini et al. (US 11462463 B2) - multi-die IC package
Sato et al. (US 20230099856 A1) - integrated circuit package module
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren A Shaw whose telephone number is (571)272-3074. The examiner can normally be reached Mon-Fri 7-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838 /THIENVU V TRAN/Supervisory Patent Examiner, Art Unit 2838
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