DETAILED ACTION
This Office action is in response to the application filed on April 30, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 05, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were filed on April 30, 2024. These drawings are accepted by the Examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Rizzolatti et al. (U.S. Pub. No. 2022/0224231 A1, reference provided as part of the Information Disclosure Statement “IDS”) in view of Yang et al. (U.S. Pub. No. 2019/0319526 A1, reference provided as part of the Information Disclosure Statement “IDS”).
In re claim 1, Rizzolatti discloses (Fig. 2) a multi-level converter (130) including:
(a) an M-level converter cell that includes:
(1) an input terminal (input terminal connected to drain of Q1 and input terminal connected to source of Q4);
(2) a set of switches series-coupled (Q1-Q4) between a voltage source (Vin) and a reference voltage (ground);
(3) an output terminal coupled to an innermost pair of the set of switches (output terminal coupled between Q2 and Q3) and configured to be coupled to an inductor (Lout);
(4) switch control inputs coupled to the set of switches (gate terminals of Q1-Q4); and
(5) at least one fly capacitor (CF1) coupled in series with certain respective switches and in parallel with switches situated in between the respective switches;
wherein the M-level converter cell is configured to transform an input voltage (Vin) applied to the input terminal to an output voltage (Vout) on the output terminal in response to control signals on the switch control inputs (control signals S1, S2, S1*, S2*);
(b) a controller (Figs. 2-3, 140) coupled to the inductor and to the switch control inputs, the controller configured to monitor the output of the M-level converter cell and dynamically generate a set of switch control input values to the M-level converter cell in response to such monitoring (Para. 0065-0072).
Rizzolatti fails to disclose (c) a sub-harmonic signal generator coupled to the controller and configured to selectively inject a sub-harmonic signal (Vramp) into a signal path (204) of the controller (180).
Yang teaches (Fig. 2) a power converter (100), comprising (c) a sub-harmonic signal generator (212) coupled to the controller (180) and configured to selectively inject a sub-harmonic signal into a signal path of the controller (180).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Rizzolatti to include a sub-harmonic signal generator coupled to the controller and configured to selectively inject a sub-harmonic signal into a signal path of the controller as disclosed in Yang to have a suitable ramp signal so as to achieve both stable operations and fast transient responses under a variety of operating conditions (Para. 0007).
In re claim 2, Rizzolatti fails to disclose wherein the controller includes a comparison device having an input coupled to the inductor, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path between the inductor and the comparison device.
Yang teaches (Fig. 2) a power converter (100), wherein the controller (180) includes a comparison device (206) having an input coupled to the inductor (coupled through the feedback terminal), and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path (204) between the inductor and the comparison device.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Rizzolatti wherein the controller includes a comparison device having an input coupled to the inductor, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path between the inductor and the comparison device as disclosed in Yang to have a suitable ramp signal so as to achieve both stable operations and fast transient responses under a variety of operating conditions (Para. 0007).
In re claim 3, Rizzolatti discloses (Fig. 3) wherein the controller includes a comparison device (310) having a reference voltage input (VREF).
Rizzolatti fails to disclose wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal at the reference voltage input.
Yang teaches (Fig. 2) a power converter (100), wherein the sub-harmonic signal generator (212) is configured to selectively inject the sub-harmonic signal at the reference voltage input (Para. 0035-0041).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Rizzolatti wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal at the reference voltage input as disclosed in Yang to have a suitable ramp signal so as to achieve both stable operations and fast transient responses under a variety of operating conditions (Para. 0007).
In re claim 4, Rizzolatti discloses (Fig. 3) wherein the controller includes a compensation circuit (340).
Rizzolatti fails to disclose wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path after the compensation circuit.
Yang teaches (Fig. 2) a power converter (100), wherein the sub-harmonic signal generator (212) is configured to selectively inject the sub-harmonic signal in the signal path after the compensation circuit (Para. 0035-0041).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Rizzolatti wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path after the compensation circuit as disclosed in Yang to have a suitable ramp signal so as to achieve both stable operations and fast transient responses under a variety of operating conditions (Para. 0007).
In re claim 5, Rizzolatti discloses (Fig. 3) wherein the controller includes a compensation circuit (340).
Rizzolatti fails to disclose wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path before the compensation circuit.
Yang teaches (Fig. 2) a power converter (100), wherein the sub-harmonic signal (212) generator is configured to selectively inject the sub-harmonic signal in the signal path before the compensation circuit (Para. 0035-0041).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Rizzolatti wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path before the compensation circuit as disclosed in Yang to have a suitable ramp signal so as to achieve both stable operations and fast transient responses under a variety of operating conditions (Para. 0007).
In re claim 6, Rizzolatti fails to disclose wherein the controller includes a pulse-width modulation generator, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path after the pulse-width modulation generator.
Yang teaches (Fig. 2) a power converter (100), wherein the controller includes a pulse-width modulation generator (208), and wherein the sub-harmonic signal generator (212) is configured to selectively inject the sub-harmonic signal in the signal path after the pulse-width modulation generator (Para. 0035-0041).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Rizzolatti wherein the controller includes a pulse-width modulation generator, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path after the pulse-width modulation generator as disclosed in Yang to have a suitable ramp signal so as to achieve both stable operations and fast transient responses under a variety of operating conditions (Para. 0007).
In re claim 14, Rizzolatti fails to disclose wherein the sub-harmonic signal is an AC waveform.
Yang teaches (Fig. 2) a power converter (100), wherein the sub-harmonic signal is an AC waveform (Figs. 7-8, Para. 0070-0073).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Rizzolatti wherein the sub-harmonic signal is an AC waveform as disclosed in Yang to have a suitable ramp signal so as to achieve both stable operations and fast transient responses under a variety of operating conditions (Para. 0007).
Allowable Subject Matter
Claims 7-13 and 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 7, the prior art of record fails to disclose or suggest “wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal when an average current through the inductor is approximately zero amps” in combination with other limitations of the claim.
Regarding to claim 8, the prior art of record fails to disclose or suggest “wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal when a light load is present on the output terminal” in combination with other limitations of the claim.
Regarding to claim 9, the prior art of record fails to disclose or suggest “wherein the sub-harmonic signal generator is configured to inject a scaled sub-harmonic signal as a function of the absolute value of the average current through the inductor” in combination with other limitations of the claim.
Regarding to claim 10, the prior art of record fails to disclose or suggest “wherein the set of switches has a switching frequency, and the sub-harmonic signal has a frequency about one-half the switching frequency of the set of switches” in combination with other limitations of the claim.
Regarding to claim 11, the prior art of record fails to disclose or suggest “wherein the set of switches has a switching frequency, and the sub-harmonic signal has a frequency less than one-half the switching frequency of the set of switches” in combination with other limitations of the claim.
Regarding to claim 12, the prior art of record fails to disclose or suggest “wherein the sub-harmonic signal enables charge balancing of the at least one fly capacitor” in combination with other limitations of the claim.
Regarding to claim 13, the prior art of record fails to disclose or suggest “wherein the sub-harmonic signal creates temporary positive and negative currents sufficient to enable charge balancing of the at least one fly capacitor” in combination with other limitations of the claim.
Regarding to claim 15, the prior art of record fails to disclose or suggest “wherein the sub-harmonic signal is an AC waveform having an average voltage of zero” in combination with other limitations of the claim.
Regarding to claim 16, the prior art of record fails to disclose or suggest “wherein the sub-harmonic signal is injected by altering the timing of a digital waveform generated by the controller that controls switching of the set of switches” in combination with other limitations of the claim.
Regarding to claim 17, the prior art of record fails to disclose or suggest “wherein the switch control inputs include a pulse-width modulated signal, and the sub-harmonic signal is injected by altering the timing of the pulse-width modulated signal” in combination with other limitations of the claim.
Regarding to claim 18, the prior art of record fails to disclose or suggest “wherein the controller is further configured to add an extra charging cycle near or at a zero-current crossing point after a discharging cycle, and add an extra discharging cycle near or at a zero-current crossing point after a charging cycle” in combination with other limitations of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAFAEL O. DE LEÓN DOMENECH whose telephone number is (571)270-0517. The examiner can normally be reached 8:00 a.m. -5:00 p.m..
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/RAFAEL O DE LEON DOMENECH/Primary Examiner, Art Unit 2838