DETAILED ACTION
Response to Arguments
Applicant’s arguments, see pg 13, filed 6 May 2026, with respect to objections to the drawings, specification, and claims have been fully considered and are persuasive. The objections to the drawings, specification, and claims have been withdrawn.
Applicant’s arguments, see pg 13 last paragraph, filed 6 May 2026, with respect to 35 U.S.C. § 112(b) rejections have been fully considered and are persuasive. The 35 U.S.C. § 112(b) rejection of Claims 17-21 have been withdrawn.
Applicant’s arguments with respect to the 35 U.S.C. § 103 rejection of claim 17 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 20 is objected to because of the following informalities:
Claim 20: recites the limitation "the comparison in the second mode" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7, 15, & 17-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 7 & 15: the limitation “comparator configurable to compare the first signal with a threshold” is not supported by the specification. Specification [0031] describes the comparison as being to “a ground voltage”. The claim uses the generic term “threshold”. While ground is also a threshold, the specification does not describe comparing the current terminal voltage to any other reference voltage. This matter was not originally disclosed and broadens the claims beyond the supported scope.
Claim 17: the limitation “comparison between a first voltage at a current terminal of the hybrid power switch circuitry and a threshold” is not supported by the specification. Specification [0031] describes the comparison as being to “a ground voltage”. The claim uses the generic term “threshold”. While ground is also a threshold, the specification does not describe comparing the current terminal voltage to any other reference voltage. This matter was not originally disclosed and broadens the claims beyond the supported scope.
Claims 18-21 depend from Claim 17 and thus have at least the same defect.
Claim 20: recites the limitations “first mode” and “second mode” where different signals are generated responsive to different inputs depending on mode. These terms do not appear in the specification, and the specification does not describe a specific operating configuration where the first signal generation changes from being responsive to the switching signal to being responsive to the comparison. The specification [0021 & 0039] describes different programmable switch configurations based on the device ratio, but does not describe a specific mode-dependent signal generation behavior.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Nagase (US 20180138904 A1), in view of Jacobson (US 9030054 B2), and further in view of Lu (US 9735771 B1).
Regarding Claim 11, Nagase teaches a apparatus (1, Fig 1) comprising: a first transistor (IGBT 20, Fig 1) and a second transistor (FET 30, Fig 1) coupled in parallel between a first current terminal and a second current terminal (20 & 30 connected in parallel between top and bottom nodes, Fig 1), the first transistor having a first transistor control terminal (gate of 20, Fig 1), and the second transistor having a second transistor control terminal (gate of 30, Fig 1); control circuitry (11-13, Fig 1) having inputs coupled to a switching signal input (driving signal, Fig 1), the first transistor control terminal (12 gets its input from the gate of 20, Fig 1), the control circuitry configurable to turn on the first transistor before the second transistor ("turn on the FET 30 as early as possible after confirming the situation in which the IGBT 20 is turned on.", Fig 1, [0030]), responsive to a switching signal at the switching signal input (20 and 30 turn on responsive to the driving signal, Fig 1, [0022]), and a second voltage at the first transistor control terminal ("12 monitors a voltage applied to the gate of the IGBT 20, and detects the situation in which the IGBT 20 is switched to an on-state when the applied voltage is larger than or equal to the predetermined voltage.", Fig 1, [0022]); a first driving circuit coupled between the control circuitry and the first transistor control terminal (11, Fig 1); and a second driving circuit coupled between the control circuitry and the second transistor control terminal (13, Fig 1).
Nagase does not teach the first current terminal, to turn off the first transistor before the second transistor, or a first voltage at the first current terminal
Jacobson teaches a conventional composite power switch gate control method (see Fig 3A&B) including the first current terminal ("controller 21 senses the voltage across the MOSFET switch 12 to determine the length of the turn-on transition time interval and compares it with a reference signal.", Col 16[7-10]), a first voltage at the first current terminal ("controller 21 senses the voltage across the MOSFET switch 12 to determine the length of the turn-on transition time interval and compares it with a reference signal.", Col 16[7-10]).
Jacobson does not teach to turn off the first transistor before the second transistor.
Lu teaches a conventional hybrid switch driving mode (see Figs 2-3) including to turn off the first transistor before the second transistor ("During the time period between times t.sub.3, t.sub.4, the upper GaN HEMT 26.sub.1 is ON and the upper Si MOSFET 34.sub.1 is OFF", Figs 2-3, Col 7[12-4]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the composite power switch gate control method in Nagase, as taught by Jacobson, as it provides the advantage of improving reliability and performance (Col 3[33-4] of Jacobson).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the hybrid switch driving mode in Nagase, as taught by Lu, as it provides the advantage of reducing switching losses which improves the converter's efficiency (Col 3[23-9] of Lu).
Regarding Claim 12, the combination of Nagase, Jacobson, and Lu discloses all of the limitations of claim 11, and further discloses wherein the switching signal is a pulse width modulation signal (19 is a digital PWM module, Fig 3B of Jacobson).
Regarding Claim 14, the combination of Nagase, Jacobson, and Lu discloses all of the limitations of claim 11, and further discloses wherein the selected ratio reflects more silicon device in comparison to the wide bandgap device, and wherein the silicon device is turned on first when the received signal to turn on the hybrid switch circuitry is asserted before turning on the wide bandgap device, and wherein the wide bandgap device remains on when the silicon device is turning off and wherein the wide bandgap device is turned off after the silicon device is turned off.
Regarding Claim 15, the combination of Nagase, Jacobson, and Lu discloses all of the limitations of claim 11, and further discloses further comprising a comparator (12 compares voltage to a threshold, Fig 1, of Nagase) configurable to compare the first voltage with a threshold ("controller 21 senses the voltage across the MOSFET switch 12 to determine the length of the turn-on transition time interval and compares it with a reference signal.", Col 16[7-10] of Jacobson), an output of the comparator coupled to an input of the control circuitry (on-enabled output of 12 is connected to 13, Fig 1, [0053] of Nagase).
Therefore, it would have been obvious to one of ordinary skill in the art before the earliest effective filing date to simply substitute the known voltage monitored by Nagase's comparator (gate voltage) with the voltage at the current terminal of Jacobson, to obtain the predictable result of detecting whether the first transistor has entered conduction and triggering of the second transistor accordingly, see (KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385).
Regarding Claim 16, the combination of Nagase, Jacobson, and Lu discloses all of the limitations of claim 11, and further discloses further comprising a comparator configurable to compare the second voltage with a threshold (12 compares gate voltage of 20 to Vth, Fig 1, [0053] of Nagase), an output of the comparator coupled to an input of the control circuitry (on-enabled output of 12 is connected to 13, Fig 1, [0053] of Nagase), and the control circuitry is configurable to turn off the second transistor responsive to a state of the output of the comparator (when on-enabled output of 12 is terminated FET 30 turns off, Fig 1, [0053] of Nagase).
Claims 17-19 & 21 are rejected under 35 U.S.C. 103 as being unpatentable over Nagase (US 20180138904 A1), in view of Jacobson (US 9030054 B2).
Regarding Claim 17, Nagase teaches a method comprising: receiving a switching signal to turn on a hybrid power switch circuitry including a first transistor and a second transistor (20 and 30 receive switching signals from 11-13 according to the driving signal, Fig 1); generating a first signal to turn on or off the first transistor responsive to the switching signal (11 generates the gate voltage of 20 responsive to the driving signal, Fig 1); and generating a second signal to turn on the second transistor (13 generates the gate voltage of 30 responsive to the driving signal and output of 12, Fig 1).
Nagase does not teach responsive to a comparison between a first voltage at a current terminal of the hybrid power switch circuitry and a threshold.
Jacobson teaches a conventional composite power switch gate control method (see Fig 3A&B) including a comparison between a first voltage at a current terminal of the hybrid power switch circuitry and a threshold ("controller 21 senses the voltage across the MOSFET switch 12 to determine the length of the turn-on transition time interval and compares it with a reference signal.", Col 16[7-10]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the composite power switch gate control method in Nagase, as taught by Jacobson, as it provides the advantage of improving reliability and performance (Col 3[33-4] of Jacobson).
Regarding Claim 18, the combination of Nagase and Jacobson discloses all of the limitations of claim 17, and further discloses wherein the threshold is a first threshold (V1REF, Fig 3B of Jacobson), and the method further comprises generating a third signal to turn off the second transistor responsive to a comparison between a second voltage at a control terminal of the first transistor and a second threshold (12 generates on-enabled signal to turn off 30 responsive to the gate signal to 20 being compared to a predetermined threshold, Fig 1, [0022] of Nagase).
Regarding Claim 19, the combination of Nagase and Jacobson discloses all of the limitations of Claim 17 except for wherein the threshold is explicitly a ground voltage. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Knoedgen, Chen, and Bianco, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Moreover, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPT 215 (CCPA 1980).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Nagase and Jacobson to include wherein the threshold is a ground voltage by connecting the reference signal connection V1REF to ground since ground is the simplest and most natural reference for determining when a power transistor has entered full conduction, and therefore ensuring the first transistor is fully saturated before activating the second transistor to maximize the current-sharing benefit of the hybrid switch configuration.
Regarding Claim 21, the combination of Nagase and Jacobson discloses all of the limitations of claim 17, and further discloses wherein the first transistor includes a silicon device (20 is a silicon IGBT, Fig 1 of Nagase), and the second transistor includes a wide bandgap device (30 is a wide bandgap semiconductor, Fig 1, [0024] of Nagase).
Allowable Subject Matter
Claims 1-6 & 8-10 are allowed.
Claims 7 & 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(a), set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1-16 & 18 would be allowable if rewritten to overcome the Claim Objections set forth in this Office action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.C.C./Examiner, Art Unit 2838
/GARY L LAXTON/Primary Examiner, Art Unit 2838 6/11/2026
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