DETAILED ACTION
This office action is in response to the response filed on 05/12/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The listing of references in the specification is not a proper information disclosure statement. 37 CFR 1.98(b) requires a list of all patents, publications, or other information submitted for consideration by the Office, and MPEP § 609.04(a) states, "the list may not be incorporated into the specification but must be submitted in a separate paper." Therefore, unless the references have been cited by the examiner on form PTO-892, they have not been considered.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in LU 504159 on May 8, 2023. It is noted, however, that applicant has not filed a certified copy of the Foreign application as required by 37 CFR 1.55.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang US 2023/0238876 in view of Fesseler DE 102020116889 (Fesseler US 2023/0246541 used for Translation purposes).
Regarding Claim 1, Zhang teaches (Figures 1-4 and 16) a PFC network circuit (10) with a half-bridge (121-122) for converting an AC power supply voltage (9) to both a lower and a higher DC output voltage (fig. 2) in compliance with PFC standards (high efficiency), the PFC network circuit (10) comprising: three phases (a-c); a rectifier (11) comprising three inputs; a first and a second transistor (Tdc switches), controlled by a control unit (controller see fig. 16); a midpoint (S) which is arranged between the first and second transistor (Tdc switches ); a star point (k) comprising three star capacitors (15); a capacitor (Ccm) connected to the midpoint and a reference potential (S and K), which can be either the zero potential of the PFC network circuit or the star point of the star capacitors (15); an output capacitor (Coutp), an output coil (Ldc), a diode (par. 56) and a string capacitor (Coutn), wherein the output capacitor, the output coil, the diode and the string capacitor are provided at an output region (right side of converter) of the PFC network circuit; and three storage chokes (Lm), each of which is connected to one of the three phases and one of the three inputs of the rectifier (See fig. 1); and wherein the control unit (controller) is arranged to control the first transistor and the second transistor (Tdc switches) so as to convert an AC power supply voltage into a stepped-up or stepped-down DC output voltage (see fig. 2) depending on a polarity of string voltages (see fig. 16 with 22, Sector circuit and 24). (For Example: Par. 56-60, 86-88 and 94-96)
Zhang does not teach wherein the capacitor is configured to serve as an adjustable voltage source by selectively charging and discharging by controlling the first and second transistors and to adjust a voltage difference across the three storage chokes in order to meet PFC standards; and wherein controlling of the first and second transistors is conducted by the control unit by positive and negative controlling.
Fesseler teaches (Figures 1-3, 6-7, 12, 13-16) wherein the capacitor (Cs) is configured to serve as an adjustable voltage source by selectively charging and discharging by controlling the first and second transistors (St) and to adjust a voltage difference across the three storage chokes (par. 63 and claim 17) in order to meet PFC standards (par. 12); and wherein controlling of the first and second transistors (St) is conducted by the control unit by positive and negative controlling (Fig. 16, positive and negative drive). (For Example: Par. 63-65 and 76-86)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhang to include wherein the capacitor is configured to serve as an adjustable voltage source by selectively charging and discharging by controlling the first and second transistors and to adjust a voltage difference across the three storage chokes in order to meet PFC standards; and wherein controlling of the first and second transistors is conducted by the control unit by positive and negative controlling, as taught by Fesseler to provide a low-cost circuit with simple control that draws largely sinusoidal phase currents from a three-phase supply network, while maintaining limits on harmonic currents of PFC standards.
Regarding Claim 2, Zhang teaches (Figures 1-4 and 16) the circuit.
Zhang does not teach wherein the diode comprises at least one of a positive diode in the positive path, a negative diode in the negative path, or the positive diode in the positive path and the negative diode.
Fesseler teaches (Figures 1-3, 6-7, 12, 13-16) wherein the diode (Fig. 13, D+/-) comprises at least one of a positive diode (D+) in the positive path, a negative diode in the negative path (D-), or the positive diode in the positive path and the negative diode. (For Example: Par. 63-65 and 76-86)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhang to include wherein the diode comprises at least one of a positive diode in the positive path, a negative diode in the negative path, or the positive diode in the positive path and the negative diode, as taught by Fesseler to provide a low-cost circuit with simple control that draws largely sinusoidal phase currents from a three-phase supply network, while maintaining limits on harmonic currents of PFC standards.
Regarding Claim 3, Zhang teaches (Figures 1-4 and 16) wherein the string capacitor (Coutn) comprises at least one of a positive-strand capacitor in the positive string, a negative-strand capacitor in the negative string (Coutn) or the positive-strand capacitor in the positive string and the negative-strand capacitor in the negative string. (For Example: Par. 56-60, 86-88 and 94-96)
Regarding Claim 4, Zhang teaches (Figures 1-4 and 16) wherein the output coil (Ldc) comprises at least one of a positive output coil in the positive path (Ldcp), a negative output coil in the negative path (Ldcn) or the positive output coil in the positive path and the negative output coil. (For Example: Par. 56-60, 86-88 and 94-96)
Regarding Claim 5, Zhang teaches (Figures 1-4 and 16) a circuit.
Zhang does not teach further comprising a positive decoupling diode, provided at the output region of the network circuit in the positive path and a negative decoupling diode, provided at the output region of the network circuit in the negative path.
Fesseler teaches (Figures 1-3, 6-7, 12, 13-16) a positive decoupling diode (DL+ in Fig. 6), provided at the output region of the network circuit (at MPN) in the positive path and a negative decoupling diode (DL-), provided at the output region of the network circuit in the negative path. (For Example: Par. 63-65 and 76-86)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhang to include a positive decoupling diode, provided at the output region of the network circuit in the positive path and a negative decoupling diode, provided at the output region of the network circuit in the negative path, as taught by Fesseler to provide a low-cost circuit with simple control that draws largely sinusoidal phase currents from a three-phase supply network, while maintaining limits on harmonic currents of PFC standards.
Regarding Claims 6-7, Zhang teaches (Figures 1-4 and 16)the circuit.
Zhang does not teach wherein the PFC network circuit is formed as multi-channel; and in which the channels of the multi-channel network circuit can be operated synchronously or offset according to the interleave principle.
Fesseler teaches (Figures 1-3, 6-7, 12, 13-16) wherein the PFC network circuit (Fig. 12) is formed as multi-channel; and in which the channels of the multi-channel network circuit can be operated synchronously (par. 74) or offset according to the interleave principle.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhang to include wherein PFC the network circuit is formed as multi-channel; and in which the channels of the multi-channel network circuit can be operated synchronously or offset according to the interleave principle, as taught by Fesseler to provide a low-cost circuit with simple control that draws largely sinusoidal phase currents from a three-phase supply network, while maintaining limits on harmonic currents of PFC standards at different phases.
Regarding Claims 8 and 10, Zhang teaches (Figures 1-4 and 16) a method of converting an AC power supply voltage (9) to both a lower and a higher DC output voltage (see fig. 2) while complying with PFC standards (high efficiency) on using a PFC network circuit (10), the method comprising: controlling of a first and a second transistor (at 131 and 122); charging and discharging a capacitor (Ccm) depending on the controlling (done by the controller in fig. 16); generating a capacitor voltage in the capacitor (voltage at capacitor); and wherein the DC output voltage (at Vout) is stepped up or down with respect to the AC power supply voltage depending on the controlling (with controller). (For Example: Par. 56-60, 86-88 and 94-96)
Zhang does not teach influencing a voltage difference at three storage chokes by the capacitor voltage of the capacitor; and extracting sinusoidal phase currents from a supply network, wherein limit values for harmonic currents of the PFC standard are complied with; wherein the controlling comprises a positive and a negative controlling and takes into account a polarity of string voltages; wherein coil voltages of the storage chokes correspond to the voltage differences between the capacitor voltage and the respective AC power supply voltage as a result of charging and discharging.
Fesseler teaches (Figures 1-3, 6-7, 12, 13-16) influencing a voltage difference at three storage chokes by the capacitor voltage of the capacitor (par .63); and extracting sinusoidal phase currents from a supply network(par. 62), wherein limit values for harmonic currents of the PFC standard are complied with(claim 17 and par. 12); wherein the controlling comprises a positive and a negative controlling (fig. 16, positive and negative drive) and takes into account a polarity of string voltages; wherein coil voltages of the storage chokes correspond to the voltage differences between the capacitor voltage and the respective AC power supply voltage as a result of charging and discharging (Claim 17 & par. 13 and 63). (For Example: Par. 63-65 and 76-86)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhang to include influencing a voltage difference at three storage chokes by the capacitor voltage of the capacitor; and extracting sinusoidal phase currents from a supply network, wherein limit values for harmonic currents of the PFC standard are complied with; wherein the controlling comprises a positive and a negative controlling and takes into account a polarity of string voltages; wherein coil voltages of the storage chokes correspond to the voltage differences between the capacitor voltage and the respective AC power supply voltage as a result of charging and discharging, as taught by Fesseler to provide a low-cost circuit with simple control that draws largely sinusoidal phase currents from a three-phase supply network, while maintaining limits on harmonic currents of PFC standards.
Regarding Claim 9, Zhang teaches (Figures 1-4 and 16) wherein the first transistor and second transistor (at 121-122) are controlled in such a way that the DC output voltage (Vout) is regulated to a desired value depending on the load (Fig. 2) (For Example: Par. 56-60, 86-88 and 94-96)
Zhang does not teach the first and second transistors controlled with at least one of a switch-on duration, a short-circuit duration and a switch-off duration of the first and second transistors serving as degrees of freedom.
Fesseler teaches (Figures 1-3, 6-7, 12, 13-16) the first and second transistors (St) controlled with at least one of a switch-on duration (Te), a short-circuit duration (Tk) and a switch-off duration (Ta) of the first and second transistors serving as degrees of freedom. (For Example: Par. 78-82)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhang to include the first and second transistors controlled with at least one of a switch-on duration, a short-circuit duration and a switch-off duration of the first and second transistors serving as degrees of freedom, as taught by Fesseler to provide a low-cost circuit with simple control that draws largely sinusoidal phase currents from a three-phase supply network, while maintaining limits on harmonic currents of PFC standards.
Response to Arguments
Applicant’s arguments filed 05/12/2026 have been fully considered but they are not persuasive.
Applicant Argued that “Claim 1 requires a midpoint arranged between the first and second transistor, with a capacitor connected to the midpoint and a reference potential, wherein the capacitor charges and discharges through control of those two transistors to generate an adjustable voltage that directly influences the coil voltages of the three storage chokes LL1, LL2, LL3 at the rectifier input”. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Zhang teaches the structure of the midpoint arrangement as recited above and the charging and discharging function is met by the Fesseler reference.
Applicant argued that “In response to applicant's argument that “A person of ordinary skill in the art would recognize that introducing Fesseler's capacitor mechanism into Zhang would create conflicting control of the AC-side currents - with Zhang's CSR stage attempting to shape phase currents through 3/3-PWM or 2-PWM, and Fesseler's capacitor mechanism simultaneously attempting to shape the same phase currents through a different mechanism. These two control mechanisms are architecturally incompatible and would not yield a functional converter.”, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Examiner would also like to point out that the structure of the Fesseler reference and the Zhang reference is very similar as can be seen in Figure 1 of Fesseler the MPN circuitry where the capacitor is located is connected to the BS or KS circuit where the star connected capacitors are located. Zhang’s Figure 1 has the same circuitry with a Ccm capacitor connected between the TDC switches and the Cin capacitors, the examiner does not see the structural difference that would change the system of Zhang. Applicant argued that “Further, the Examiner proposes the combination to "provide a low-cost circuit with simple control that draws largely sinusoidal phase currents from a three-phase supply network, while maintaining limits on harmonic currents of PFC standards" (Office Action, page 6).” The motivation to combine both references which both provide a function for AC to DC conversion and having a PFC operation is mentioned in par. 12 of Fesseler and recites “[0012] The objective of the present invention is thus to provide a low-cost circuit with simple control that draws largely sinusoidal phase currents from a three-phase supply network, while maintaining limits on harmonic currents of PFC standards.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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