Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending (claim 3 withdrawn).
Election/Restrictions
3. Claim 3 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/25/2026.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 states that the isolation structure comprises a first portion and a second portion. This is considered indefinite in view of claim 2 subject matter (of which claim 4 depends). Claim 2 states that the isolation structure is a one-piece structure. However, claim 4 describes the one piece isolation structure to instead be comprised of two portions contradicting the subject matter of claim 2.
Support for the subject matter of claim 2 can be found in figure 2 and paragraph [0086] respectively depicting and describing the isolation structure 500 as a single piece with no portions. Support for the subject matter of claim 4 can be found in figure 10 of the current application. Said figure depicts the isolation structure 500 to comprise first and second portions 510+520. In view of the election of figure 10 and in view of contradicting components in view of figures 2 and 10 it is suggested to remove the subject matter of claim 2 “and the first shielding structure comprises a one-piece structure” to overcome this rejection.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 3-8, and 11-20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Bang et al. (US Patent Application Publication 2021/0083013), herein after referred to as Bang.
Regarding independent claim 1, Bang discloses a display panel (Figure 4 DP) with a display area (DA) and a non-display area (NDA), the display panel (DA) comprising:
an array base plate (Figure 9 SUB);
a light-emitting layer (EML) arranged on the array base plate (SUB) and comprising a plurality of light-emitting units (OLED) (Figure 4 depicts a plurality of pixels PX disposed in the display area DA. Figure 5 depicts each pixel PX to comprise an OLED. Figure 9 depicts a cross-sectional view of the display module including display area DA and non-display area NDA depicting only one of the plurality of OLEDs in the display area DA.);
an isolation structure (PDL) located in the display area (DA), the isolation structure (PDL) being arranged (indirectly) on the array base plate (SUB) and comprising a plurality of isolation openings (Figure 9 depicts openings between PDL corresponding to AE+EML of the OLED, herein after referred to as AE+EML), the light-emitting units (OLED) being located within the isolation openings (Figure 9 depicts openings between PDL corresponding to AE+EML of the OLED, herein after referred to as AE+EML);
a first shielding structure (SHL described in [0155] to block noise from driving circuit GDC towards touch sensing layer TS) located in the non-display area (NDA) and arranged in the same layer (30) as at least a portion of the isolation structure (PDL) (Both SHL and PDL both disposed on 30 and considered within the same layer comprised of 40+0L); and
a touch control component (SL2) at least partially located at a side (upper side/above) of the first shielding structure (SHL) away from the array base plate (SUB).
Regarding claim 2, Bang discloses the display panel according to claim 1, wherein each of at least a portion of the isolation structure (Figure 9 PDL) and at least a portion of the first shielding structure (SHL) comprises an electrically conductive material (CE) (In the interpretation that PDL and SHL comprise “an electrically conductive material” implying the same material for both: electrically conductive material CE is in direct contact with PDL and indirectly with SHL via E-CNT as depicted in figure 9 [0150]; in the interpretation that PDL comprises an electrically conductive material and SHL comprises an electrically conductive material that may be different: PDL is in direct contact with AE, E-CNT, and CE described in [0155] to electrically conduct power E-VSS while SHL is connected to E-VSS via E-CNT [0150]); and the isolation structure (PDL) and the first shielding structure (SHL) are arranged in a same layer (30), and each of the isolation structure (PDL) and the first shielding structure (SHL) comprises a one-piece structure (see 112 above) (Figure 9 depicts SHL as an electrode of a single material (one-piece structure) and PDL is also depicted as a single material (one-piece structure).).
Regarding claim 4, Bang discloses the display panel according to claim 2, wherein the isolation structure (Figure 9 PDL) comprises a first isolation portion (PDL) and a second isolation portion (CE) (Support for the subject matter can be found in applicant’s figure 10 [0103] isolation portion 510 is electrically conductive) arranged at a side (upper) of the first isolation portion (PDL) away from the array base plate (SUB), an orthographic projection of the first isolation portion (PDL) on the array base plate (SUB) is located within an orthographic projection of the second isolation portion (CE) on the array base plate (SUB) (figure 9 reference depiction of a portion of CE directly above within the overlap of PDL), the first shielding structure (SHL) comprises a first shielding portion (SHL) and a second shielding portion (E-CNT) arranged at a side (upper) of the first shielding portion (SHL) away from the array base plate (SUB), and an orthographic projection of the first shielding portion (SHL) on the array base plate (SUB) is located within an orthographic projection of the second shielding portion (E-CNT) on the array base plate (SUB) ([0155] SHL and E-CNT are arranged to purposely partially overlap);
the first shielding portion and the first isolation portion are arranged in a same layer and formed with a same material, or the second shielding portion (E-CNT) and the second isolation portion (CE) are arranged in a same layer (40) and formed with a same material ([0150] CE and E-CNT are electrically connected); and
the first shielding portion (SHL) and the first isolation portion (PDL) comprise the electrically conductive material (CE) ([0150]).
Regarding claim 5, Bang discloses the display panel according to claim 1, wherein the first shielding structure (SHL) is connected to a direct current voltage signal end (Figure 4 E-VSS [0150]) of the display panel (Figure 4 DP); and a signal line of the direct current voltage signal end (E-VSS) comprises at least one of a touch control ground signal line, an initialization signal line, a negative supply voltage signal line, or a positive supply voltage signal line ([0150] describes E-VSS to be connected to electrode CE. CE is depicted in figure 9 and [0116] to be utilized with AE and EML for the OLED. This implies CE to regard a common electrode supported in figure of figure 5 depicting the cathode of OLED connected to ELVSS implies E-VSS. This describes E-VSS to regard a positive or negative supply voltage signal line.).
Regarding claim 6, Bang discloses the display panel according to claim 1, wherein the first shielding structure (Figure 9 PDL) comprises a plurality of first shielding openings (AE+EML);
a plurality of the first shielding (SHL) openings (TH1) are arranged at intervals in a first direction (DR2) or a second direction (DR3), wherein the first direction is intersected with the second direction (axis depicted in figure 9);
an orthographic projection of a portion of the touch control component (SL2) located in the non-display area (NDA) on the array base plate (SUB) is located within an orthographic projection of the first shielding structure (SHL) on the array base plate (SUB) (depicted in figure 9 and [0155] TH1 purposely overlaps portions of SL2 and E-CNT); and
the array base plate (SUB) further comprises a drive circuit (GDL) ([0143]), and an orthographic projection of the drive circuit (GDL) located in the non-display area (NDA) on the array base plate (SUB) is located within the orthographic projection of the first shielding structure (SHL) on the array base plate (SUB) (depicted in figure 9 and described in [0155]).
Regarding claim 7, Bang discloses the display panel according to claim 6, wherein the display panel (Figure 4 DP) further comprises a second shielding structure (figure 9 E-CNT) located at a side (upper) of the first shielding structure (SHL) facing the array base plate (SUB), an orthographic projection of at least a portion of the second shielding structure (E-CNT) in a thickness direction (DR3) of the display panel (DP) covers the first shielding (SHL) openings (TH1) (depicted in figure 9 and described in [0155]).
Regarding claim 8, Bang discloses the display panel according to claim 7, wherein the display panel (figure 4 DP) further comprises a pixel (PX) defining layer (figure 9 DP-OLED) arranged at a side (upper) of the array base plate (SUB), the pixel defining layer (DP-OLED) comprises one or more pixel defining portions (PDL+VAL) and a plurality of pixel openings (AM+EML) defined by the pixel defining portions (Figure 9 depicts openings between PDL corresponding to AE+EML of the OLED, herein after referred to as AE+EML); and
the pixel defining portions (PDL+VAL) further define a plurality of third shielding openings (VAL) located in the non-display area (NDA), an orthographic projection of at least a portion of the second shielding structure (E-CNT) in the thickness direction (DR3) of the display panel (DP) covers the third shielding openings (Figure 9 depicts E-CNT covering VAL [0151]).
Regarding claim 11, Bang discloses the display panel according to claim 7, wherein the second shielding structure (E-CNT) is arranged between the first shielding structure (SHL) and the drive circuit (GDL) of the array base plate (SUB), an orthographic projection of at least a portion of the drive circuit (GDL) on the array base plate (SUB) is located within an orthographic projection of the second shielding structure (E-CNT) on the array base plate (SUB) (depicted in figure 9 and [0155] GDL overlaps E-CNT).
Regarding claim 12, Bang discloses the display panel according to claim 11, wherein the display panel (DP) further comprises a first electrode layer (AE) arranged at a side (upper) of the array base plate (SUB), and the first electrode layer (AE) comprises a plurality of first electrodes (AE) arranged within the isolation openings (AE+EML).
Regarding claim 13, Bang discloses the display panel according to claim 12, wherein at least a portion of the second shielding structure (E-CNT) is arranged in the same layer (40) as the first electrode (AE), or at least a portion of the second shielding structure (E-CNT) is arranged in the same layer (20) as at least a portion of a power signal line (E-VSS) of the display panel (DP), or at least a portion of the second shielding structure (E-CNT) is arranged in the same layer (30) as at least a portion of a data signal line (410) (Figure 6 [0113] 410 is considered data line DL depicted in figure 9 to be disposed on layer 30 of which E-CNT is partially arranged (VAL and at direct connection with SHL)) of the display panel (DP).
Regarding claim 14, Bang discloses the display panel according to claim 12, wherein at least a portion of the second shielding structure (Figure 9 E--CNT) is arranged in the same layer (20) as at least a portion of a power signal line (E-VSS [0150]) of the display panel (DP), or at least a portion of the second shielding structure (E-CNT) is arranged in the same layer (30) as at least a portion of a data signal line (410) of the display panel (DP); and the second shielding structure (E-CNT) and the first electrode (AE) are arranged in a same layer (40) and formed with a same material ([0150]).
Regarding claim 15, Bang discloses the display panel according to claim 1, wherein the display panel (DP) further comprises a second electrode layer (CE) arranged in the display area (DA), and the second electrode layer (CE) comprises a plurality of second electrodes (CE) arranged within the isolation openings (AE+EML) (Figure 4 depicts a plurality of pixels PX disposed in the display area DA. Figure 5 depicts each pixel PX to comprise an OLED. Figure 9 depicts a cross-sectional view of the display module including display area DA and non-display area NDA depicting only one of the plurality of OLEDs in the display area DA. Each OLED comprises CE.), and the second electrode (CE) being located at a side (upper) of the light-emitting unit (OLED) away from the array base plate (SUB).
Regarding claim 16, Bang discloses a display apparatus (Figure 1 DD) comprising the display panel (Figure 4 DP) according to claim 1 (see rejection of claim 1).
Regarding independent claim 17, Bang discloses a display panel (Figure 4 DP) with a display area (DA) and a non-display area (NDA), the display panel (DP) comprising:
an array base plate (Figure 9 SUB);
a light-emitting layer (EML) arranged on the array base plate (SUB) and comprising a plurality of light-emitting units (OLED) (Figure 4 depicts a plurality of pixels PX disposed in the display area DA. Figure 5 depicts each pixel PX to comprise an OLED. Figure 9 depicts a cross-sectional view of the display module including display area DA and non-display area NDA depicting only one of the plurality of OLEDs in the display area DA.);
a shielding layer (SHL described in [0155] to block noise from driving circuit GDC towards touch sensing layer TS) located in the non-display area (NDA) and arranged at a side (bottom 40) of the light-emitting layer (EML) facing the array base plate (SUB), the shielding layer (SHL) comprising a first shielding layer (SHL) and a second shielding layer (E-CNT) located at a side (upper) of the first shielding layer (SHL) away from the light-emitting layer (EML); and
a touch control component (SL2) at least partially located at a side (upper) of the shielding layer (SHL) away from the array base plate (SUB).
Regarding claim 18, Bang discloses the display panel according to claim 17, wherein the shielding layer (SHL) is arranged between the touch control component (SL2) and a driving circuit (GDL) of the array base plate (SUB), an orthographic projection of at least a portion of the drive circuit (GDL) on the array base plate (SUB) is located within an orthographic projection of the shielding layer (SHL) on the array base plate (SUB) (depicted in figure 9 to overlap).
Regarding claim 19, Bang discloses the display panel according to claim 18, wherein the display panel (DP) further comprises a first electrode layer (AE) arranged at a side (upper) of the array base plate (SUB), and first electrode layer (AE) comprises a plurality (1 per pixel PX) of first electrodes (AE) arranged between the light-emitting units (OLED) and the array base plate (SUB); and
at least a portion of the shielding layer (SHL) is arranged in the same layer (30) as the first electrode (AE), or at least a portion of the shielding layer (SHL) is arranged in the same layer (20) as at least a portion of a power signal line (E-VSS) of the display panel (DP), or at least a portion of the shielding layer (SHL) is arranged in the same layer (30) as at least a portion of a data signal line (410) of the display panel (DP).
Regarding claim 20, Bang discloses the display panel according to claim 17, wherein the shielding layer (SHL) comprises one or more air holes (TH1+TH2); and
each of the first shielding layer (SHL) and the second shielding layer (E-CNT) comprises the air hole (TH1+TH2), wherein an orthographic projection of at least a portion of the first shielding layer (SHL) in a thickness direction (DR3) of the display panel (DP) covers the air hole (TH2) in the second shielding layer (E-CNT) (depicted in figure 9 and [0155]), or an orthographic projection of at least a portion of the second shielding layer (E-CNT) in the thickness direction (DR3) of the display panel (DP) covers the air hole (Th1) in the first shielding layer (SHL) (depicted in figure 9 and [0155]).
Allowable Subject Matter
6. Claims 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 9, Bang discloses the display panel according to claim 7, wherein the second shielding structure (E-CNT) comprises an electrically conductive material (CE) ([0150]);
the second shielding structure (E-CNT) is connected to a direct current voltage signal end (Figure 4 E-VSS [0150]) of the display panel (DP);
a signal line of the direct current voltage signal end (E-VSS) comprises at least one of an initialization signal line, a negative supply voltage signal line, or a positive supply voltage signal line ([0150] describes E-VSS to be connected to electrode CE. CE is depicted in figure 9 and [0116] to be utilized with AE and EML for the OLED. This implies CE to regard a common electrode supported in figure of figure 5 depicting the cathode of OLED connected to ELVSS implies E-VSS. This describes E-VSS to regard a positive or negative supply voltage signal line.);
the second shielding structure (E-CNT) comprises a plurality of second shielding openings (TH2), an orthographic projection of at least a portion of the first shielding structure (SHL) in the thickness direction (DR3) of the display panel (DP) covers the second shielding openings (TH2) (depicted in figure 9 and described in [0155]);
a plurality of the second shielding openings (TH2) are arranged at intervals (intervals depicted in figure 9) in the first direction (DR2) or the second direction;
the orthographic projection of the first shielding structure (SHL) on the array base plate (SUB) is located within (partially) an orthographic projection of the second shielding structure (E-CNT) on the array base plate (SHL) ([0155]), or the orthographic projection of the first shielding structure (SHL) on the array base plate (SUB) overlaps (partially) the orthographic projection of the second shielding (E-CNT) structure on the array base plate (SUB) ([0155]); and
Bang does not specifically disclose an orthographic projection of an inner wall of the second shielding opening on the array base plate and an orthographic projection of an inner wall of the first shielding opening on the array base plate is separated by a preset spacing greater than or equal to 20 micrometers.
Conclusion
7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US Patent Application 2022/0262866) figure 14 depicts an arrangement of shield electrodes.
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/CHRISTOPHER E LEIBY/Primary Examiner, Art Unit 2621
