Prosecution Insights
Last updated: May 29, 2026
Application No. 18/650,918

CIRCUIT MODULE

Non-Final OA §103
Filed
Apr 30, 2024
Priority
Nov 01, 2021 — JP 2021-178932 +1 more
Examiner
NG, SHERMAN
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co. Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
405 granted / 536 resolved
+7.6% vs TC avg
Strong +16% interview lift
Without
With
+16.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
1 currently pending
Career history
543
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
87.4%
+47.4% vs TC avg
§102
11.2%
-28.8% vs TC avg
§112
0.2%
-39.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 536 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed in present Application No. 18/650,918 filed on 04/30/2024. Information Disclosure Statement The information disclosure statement filed 04/30/2024 has been submitted for consideration by the Office. It has been placed in the application file and the information referred to therein has been considered. Allowable Subject Matter Claims 5-11, 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kuruyama et al. (US 2020/0008301) in view of Ogawa et al. (US 2016/0073499). Regarding claim 1, Kuruyama discloses (in Fig. 9) a circuit module comprising: a substrate [1] including a first main surface [bottom surface of 1] and a second main surface [top surface of 1]; a resin layer [5] on the first main surface [bottom surface of 1] of the substrate [1]; an electronic component [4] on the first main surface [bottom surface of 1] or the second main surface [top surface of 1] of the substrate [1]; a penetrating portion [opening portion formed in resin layer 5] penetrating the resin layer [5] in a thickness direction; a first conductor [3a2] being a pillar conductor [opening portion formed in resin layer 5] present in the penetrating portion [opening portion formed in resin layer 5], the first conductor [3a2] including a first bottom [top surface of 3a2] closer to the substrate [5] and a second bottom [bottom surface of 3a2] inward of an outer surface [P3] of the resin layer [5]; a second conductor [3b1] being a metal film covering at least a portion of a side surface of the first conductor [3a2]; and a solder bump [3c] covering an opening of the penetrating portion [opening portion formed in resin layer 5] adjacent to the outer surface [P3] of the resin layer [5], the solder bump [3c] including a portion present in the penetrating portion [opening portion formed in resin layer 5] and electrically connected to the second bottom [bottom surface of 3a2] of the first conductor [3a2] in the penetrating portion [opening portion formed in resin layer 5]. Kuruyama does not disclose the second conductor including a portion extending continuously from the side surface of the first conductor to a same plane with the outer surface of the resin layer. Ogawa teaches (in Fig. 2) the second conductor [6] including a portion extending continuously from the side surface of the first conductor [5a] to a same plane with the outer surface [bottom surface of 7a] of the resin layer [7a]. Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit module of Kuruyama to have the second conductor including a portion extending continuously from the side surface of the first conductor to a same plane with the outer surface of the resin layer, as taught by Ogawa, in order to protect the first conductor against corrosion. Regarding claim 2, Kuruyama, as applied to claim 1, further discloses (in Fig. 9) wherein the second bottom [bottom surface of 3a2] of the first conductor [3a2] is in direct contact with the solder bump [3c]. Regarding claim 3, Kuruyama, as applied to claim 2, further discloses (in Fig. 9) wherein the second conductor [3b1] comprises a metal material harder than the first conductor [3a2] (See paragraph 0104: “For example, the metal column 3a.sub.2 is constituted of a metal material selected from Cu, a Cu alloy, and the like, the second plating film 3b.sub.1 is constituted of a metal material selected from Ni, an Ni alloy, and the like, and the covering film 3b.sub.2 is constituted of a metal material selected from Au, an Au alloy, and the like.” Nickel is harder than copper). Regarding claim 4, Kuruyama, as applied to claim 2, further discloses (in Fig. 9) a third conductor [3b2] being a metal film covering at least a portion of a side surface of the second conductor [3b1]. Regarding claim 12, Kuruyama, as applied to claim 3, further discloses (in Fig. 9) a third conductor [3b2] being a metal film covering at least a portion of a side surface of the second conductor [3b1]. Communication Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHERMAN NG whose telephone number is (571)270-3131. The examiner can normally be reached Mon-Fri 10AM-6PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHERMAN NG/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Apr 30, 2024
Application Filed
Apr 14, 2026
Examiner Interview (Telephonic)
Apr 21, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
92%
With Interview (+16.5%)
2y 4m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 536 resolved cases by this examiner. Grant probability derived from career allowance rate.

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