Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Youssef (CN 105009448 A).
In regard to Claim 15:
Youssef discloses, in Figure 6, a first transistor (534) configured to amplify an input radio frequency (RF) (RFin1) in a first frequency band (paragraph 51, lines 8-10); a second transistor (544, common-source transistor) configured to amplify an input RF signal (RFin2) in a second frequency band (paragraph 51, lines 8-12); a third transistor (536, common-grid transistor) configured to amplify an output RF signal (RFout1) of the first transistor (534, common-source transistor), and configured to turn off when the first transistor turns off (Paragraph 34, lines 12-14.); and a fourth transistor (546, common-grid transistor) configured to amplify an output RF signal (RFout2) of the second transistor (544, common-source transistor), and configured to turn off when the second transistor turns off (Paragraph 34, lines 12-14).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Youssef (CN 105009448 A), in view of Floyd (US 6930546 B2).
In regard to Claim 1:
Youssef discloses, in Figure 6, a low noise amplifier (Figure 6, 600) comprising a first transistor (Youssef; 534) configured to amplify an input radio frequency (RF) signal (Youssef; RFin1) in a first frequency band (Paragraph 51, lines 8-10) and configured to receive a first bias voltage wherein it is an inherent property of transistors, that take in as input RF signals, to have DC bias voltages in order to switch on/off said transistor; a second transistor (Youssef; 544) configured to amplify an input RF signal (Youssef; RFin2) in a second frequency band (Paragraph 51, lines 8-12) and configured to receive a second bias voltage wherein it is an inherent property of transistors, that take in as input RF signals, to have DC bias voltages in order to switch on/off said transistor; a third transistor (Youssef; 536) configured to amplify an output RF signal (Youssef; RFout1) of the first transistor (Youssef; 534) and configured to receive a third bias voltage (Youssef; Ven1); a fourth transistor (Youssef; 546) configured to amplify an output RF signal (Youssef; RFout2) if the second transistor (Youssef; 544) and configured to receive a fourth bias voltage (Youssef; Ven3),
Youssef does not disclose a first operation mode, consisting of the second bias voltage and the fourth bias voltage and neither does it disclose the second operation mode consisting of the first and third bias voltages.
In a similar field of endeavor Floyd discloses wherein a first operation mode (gain mode operation; (Floyd; Column 6, lines 60-65), the second bias voltage and the fourth bias voltage are set to an off-voltage level (Floyd; Column 6, lines 55-60) and a second operation mode (bypass mode operation, (Floyd; Column 6, lines 60-65), the first bias voltage and the third bias voltage are set to an off-voltage level (Floyd; Column 4, lines 52-60).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the two operating modes, as taught by Floyd, in combination with the elements taught by Youssef. One would be motivated to do so because Floyd teaches that by having two operating modes to switch between allows for reduction of power consumption (Floyd; Column 4, lines 3-7 ).
In regard to Claim 2:
Combination of Youssef and Floyd discloses wherein a first operation mode (gain mode operation; (Floyd; Column 6, lines 55-60), the first bias voltages and the third bias voltage are set to an on-voltage level (Floyd; Column 7 lines 55-60, cascade pair is on), and a second operation mode (Floyd; Column 6, lines 60-65), the second bias voltage and the fourth bias voltage are on (Floyd; Column 7, lines 63-66).
In regard to Claim 3:
Combination of Youssef and Floyd further discloses wherein in the first operation mode (Floyd; gain mode operation), the first transistor (Youssef; 534) and the third transistor (Youssef; 536) are configured to perform an amplification operation, and the second transistor (Youssef; 544) and the fourth transistor (Youssef; 546) do not perform the amplification operation (Floyd; Column 8, lines 22-41, in gain mode, two transistors (M1, M2) of bypass switch are off and cascode pair (Mt, MB) is on), and in the second operation mode (Floyd; bypass mode), the second transistor (Youssef; 544) and the fourth transistor (Youssef; 546) are configured to perform the amplification operation and the first transistor (Youssef; 534) and the third transistor (Youssef; 536) does not perform the amplification operation (claim 13, bypass mode, cascode pair (MT, MB) is off and two bypass transistors (M1, M2) are on).
In regard to Claim 4:
Combination of Youssef and Floyd further discloses the first operation mode (Floyd; gain mode operation) and second operation mode (Floyd; bypass mode). Floyd does not disclose the input RF signal in a first or second frequency band. Youssef further discloses wherein the input RF signal in the first frequency band is input (Youssef, Paragraph 51), and the input RF signal in the second frequency band is input (Youssef, Paragraph 51).
In regard to Claim 5:
Youssef as modified by Floyd further discloses, in figure 6, the input RF signal (Youssef; RFin1) and the first bias voltage wherein it is an inherent property of transistors, that take in as input RF signals, to have DC bias voltages in order to switch on/off said transistor in the first frequency band (Youssef; Paragraph 51) being applied to a control terminal of the first transistor (Youssef; gate of 534), and an input RF signal (Youssef; RFin2) in the second frequency band (Youssef; Paragraph 51) and the second bias voltage wherein it is an inherent property of transistors, that take in as input RF signals, to have DC bias voltages in order to switch on/off said transistor being applied to a control terminal of the second transistor (Youssef; gate of 544).
In regard to Claim 6:
Youssef as modified by Floyd further discloses, in figure 6, a third bias voltage (Youssef; Ven1) is applied to a control terminal of the third transistor (Youssef; 536 gate), and the output RF signal (Youssef; RFout1) of the first transistor (Youssef; 534) is applied to a first terminal of the third transistor (Youssef; 536 drain), and the fourth bias voltage (Youssef; Ven3) is applied to a control terminal of the fourth transistor (Youssef; 546 gate), and the output RF signal (Youssef; RFout2) of the second transistor (Youssef; 544) is applied to a first terminal of the fourth transistor (Youssef; 546 drain).
In regard to Claim 7:
Youssef as modified by Floyd further discloses, in figure 6, a first inductor (Youssef; 522) that is connected between a first terminal of the first transistor (Youssef; 534 source) and a ground; and a second inductor (Youssef; 552) that is connected between a first terminal of the second transistor (Youssef; 544 source) and the ground.
3. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Youssef (CN 105009448 A), in view of Floyd (US 6930546 B2) as applied to claim 6 above, and further in view of Tanzer (US 20240030875 A).
In regard to Claim 8:
Yousef, in view of Floyd, does not disclose an inductor comprising a first end connected to a power supply, and a second end connected to a second terminal of the third transistor and a second terminal of the fourth transistor.
In a similar field of endeavor, Tanzer (US 20240030875 A) discloses an inductor (Tanzer; Fig. 4, 82) that comprises a first end connected to a power supply voltage (Tanzer; Vdd) and a second end connected to a second terminal of the third transistor (Tanzer; 78 drain) and a second terminal of the fourth transistor (Tanzer; 98 drain).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the inductor with the forementioned connections, taught by Tanzer, in combination with Youssef and Floyd’s low noise amplifier. One would be motivated to do so as a teaching that allows for the prevention of high-frequency RF signals from leaking into the DC power supply. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
4. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Youssef (CN 105009448 A), in view of Floyd (US 6930546 B2) and Tanzer (US 20240030875 A), in further view of Poon (US 6188209 B1).
In regard to Claim 9:
Youssef, in view of Floyd and Tanzer do not disclose a variable inductor wherein the inductance value changes depending on the mode of operation.
In a similar field of view, Poon discloses a variable inductor (Poon; Fig. 1, L1) wherein an inductance value of the inductor varies depending on the first operation mode and the second operation mode (Poon; Paragraph 9 lines 3-8).
It would have been obvious to one of ordinary skill in the art, before the effective filing date to utilize the variable inductor, taught by Poon, in combination with the previous elements of Youssef, Floyd, and Tanzer. One would be motivated to do so because Poon teaches that having an inductor that changes inductance based on mode of operation allows for the circuit to dramatically increase the rate of change of current flowing through the output (Poon; Column 1, lines 55-64.
5. Claim(s) 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Youssef (CN 105009448 A), in view of Floyd (US 6930546 B2).
In regard to Claim 10:
Youssef discloses a low noise amplifier (Figure 6, 600) comprising a first transistor (Youssef; 534) configured to amplify an input radio frequency (RF) signal (Youssef; RFin1) in a first frequency band (Youssef; Paragraph 51, lines 8-10); a second transistor (Youssef; 544) configured to amplify an input RF signal (Youssef; RFin2) in a second frequency band (Youssef; Paragraph 51, lines 8-12); a third transistor (Youssef; 536) configured to amplify an output RF signal (Youssef; RFout1) of the first transistor (Youssef; 534) and configured to receive a third bias voltage (Youssef; Ven1); a fourth transistor (Youssef; 546) configured to amplify an output RF signal (Youssef; RFout2) if the second transistor (Youssef; 544) and configured to receive a fourth bias voltage (Youssef; Ven3),
Youssef does not disclose a first operation mode or a second operation mode consisting of RF input signals in a first and second frequency band; wherein a second and fourth transistors are switched to an off-state and the third transistor amplifies an output RF signal; and wherein a first and third transistor are switched to an off-state.
In a similar field of endeavor Floyd discloses wherein a first operation mode in which the input RF signal in the first frequency band (Floyd; Paragraph 51, lines 8-10) is input, setting the second transistor (Youssef; 544) and a fourth transistor (Youssef; 546) to an off-state (Floyd; claim 1, lines 6-8), wherein a third transistor (Youssef; 536) amplifies an output RF signal (Youssef; RFout1) of the first transistor; and a second operation in which the input RF signal in the second frequency band (Youssef; Paragraph 51, lines 8-12) is input, setting the first transistor (Youssef; 534) and the third transistor (Youssef; 536) to an off-state (at least one signal amplifying transistor which may comprise of a cascode pair (Floyd; Paragraph 12), wherein the fourth transistor (Youssef; 546) amplifies an output RF signal (Youssef; RFout2) of the second transistor (Youssef; 544).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the two operating modes, as taught by Floyd, in combination with the elements of Youssef. One would be motivated to do so because Floyd teaches that by having two operating modes to switch between allows for reduction of power consumption (Column 4, lines 3-7).
In regard to Claim 11:
Combination of Youssef and Floyd further discloses a first operation mode (Floyd; gain mode operation), setting the first transistor (Youssef; 534) and the third transistor (Youssef; 536) to an on-state (Floyd; claim 1, lines 6-8) and the second operation mode (Floyd; bypass mode), setting the second transistor (Youssef; 544) and the fourth transistor (Youssef; 546) to an on-state (Floyd; claim 1, lines 6-12).
In regard to Claim 12:
Combination of Youssef and Floyd further discloses a first operation mode (Floyd; gain mode), a bias voltage of the second transistor (Youssef; 544, Xin from) is set to an off-state (Floyd; claim 1, line 6-12). And a bias voltage of the fourth transistor (Youssef; 546, Ven3) is set to an off-voltage level (Floyd; claim 1), and in the second operation mode (Floyd; bypass mode), a bias voltage of the first transistor (Youssef; 534, Xin) is set to an off-voltage (Floyd; claim 1) and a bias voltage of the third transistor (Youssef; 536, Ven1) is set to an off-voltage level (Floyd; claim 1).
In regard to Claim 13:
Combination of Youssef and Floyd further discloses a first operation mode, the bias voltage of the first transistor (Youssef; Xin, 534) is set to on-voltage level, and the bias voltage of the third transistor (Youssef; 536, Ven1) is set to an on-voltage level, and a second operation mode, the bias voltage of the second transistor (Youssef; Xin, 544) is set to on-voltage level, and bias voltage of the fourth transistor is set to on (Youssef; Ven3, 546).
In regard to Claim 14:
Combination of Youssef and Floyd further discloses a first operation mode (gain mode from Floyd) an RF signal path is formed through the first transistor (Youssef; 534) and the third transistor (Youssef; 536) and in a second operation mode, an RF signal path is formed through the second transistor (Youssef; 544) and the fourth transistor (Youssef; 546).
6. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Youssef (CN 105009448 A), in view of Floyd (US 6930546 B2).
In regard to Claim 16:
Combination of Youssef and Floyd discloses a first operation mode (Floyd; gain mode), an RF signal path is formed through the first transistor (Youssef; 534) and the third transistor (Youssef; 536), and
in a second operation (Floyd; bypass mode), and RF signal path is formed through the second transistor (Youssef; 544) and the fourth transistor (Youssef; 546).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Transistor Biasing and the Biasing of Transistors. (2013, July 25). Basic Electronics Tutorials. https://web.archive.org/web/20170801051702/http://www.electronics-tutorials.ws/amplifier/transistor-biasing.html.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMAAN JAWAD KHAN whose telephone number is (571)270-7266. The examiner can normally be reached M-Th 9-4.
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/A.J.K./Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
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