DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 24 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The new claim 24 is rejected under U.S.C. 112, first paragraph because
the disclosure as originally filed, does not provide a support for the claimed feature “the reference terminal being electrically isolated from the common source” which is added to the claim 24. However, the accompanying drawing(s) show the reference terminal electrically connected to the common source terminal. Therefore, the specification does not support the amended claim language “the reference terminal being electrically isolated from the common source”.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 24 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 24 recites the limitation “the reference terminal being electrically isolated from the common source”. However, the drawing(s) show the reference terminal electrically connected to the common source terminal. This inconsistency between the claim language and the disclosure renders the scope of the claim unclear. Because the claim and the specification are contradictory, one of the ordinary skill in the art would not be able to ascertain the metes and bounds of the claimed invention with reasonable certainty. Accordingly, the claim is indefinite under 35 U.S.C §112(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-17 and 20-24 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Kinzer et al. (US 2017/0222644 and Kinzer hereinafter)
Regarding claim 16, Kinzer discloses an integrated circuit [see fig. 3B] comprising: a bi-directional switch [Q5/Q6] coupled between a first terminal [A] and a second terminal [B], the bi-directional switch having a switch control terminal [control terminal connected to G1]; a driver circuit [G1] having a power terminal [power terminal G1 ], a reference terminal [terminal connected to C1] and a driver output [G1 output connected to gate Q5/Q6], the driver output coupled to the switch control terminal; and a bias circuit [Q7, D1, D2 and Q8] coupled between the first terminal [A] and the second terminal [B], the bias circuit having configurable to set a voltage [set a voltage at node between D1 and d2 through C1] of the reference terminal, wherein the bi-directional switch and the bias circuit are on a semiconductor die [par. 0038].
Regarding claim 17, Kinzer discloses [see fig. 3B] wherein the bias circuit comprises: a first transistor [Q7] coupled between the first terminal and a bias output [output connected to node between D1 and D2] coupled to the reference terminal, the first transistor having a first control terminal [control terminal Q7] coupled to the driver output; and a second transistor [Q8] coupled between the bias output and the second terminal, the second transistor having a second control terminal [control terminal Q8] coupled to the driver output, the first and second transistors configurable to set the voltage at the bias output and the reference terminal.
Regarding claim 20, Kinzer discloses an integrated circuit [see fig. 3B] comprising: a driver circuit [G1] for driving a bidirectional switch [Q5/Q6] between a first terminal [A] and second terminal [B], the driver circuit having a reference terminal [terminal connected to node between D1 and D2 through C1] and a driver [output G1 output connected to gate Q5/Q6]; and a bias circuit [Q7, D1, D2 and Q8] including a first circuit [Q7and D1] coupled between the first terminal and the reference terminal and a second circuit [Q8 and D2] coupled between the reference terminal and the second terminal, wherein the first circuit and the second circuit are configurable to connect the reference terminal to the first terminal responsive to the first terminal having a lower voltage level than the second terminal [par. 0042-0055].
Regarding claim 21, Kinzer discloses an integrated circuit [see fig. 3B] wherein the first switch includes a first transistor [Q7] or a first diode [D1], and the second switch includes a second transistor [Q8] or a second diode [D2].
Regarding claim 22, Kinzer discloses an integrated circuit [see fig. 3B] wherein each of the first switch and the second switch has a respective control terminal [control terminal Q7 and Q8] coupled to the driver output [via driver G1 when switches Q7 and Q8 are closed].
Regarding claim 23, Kinzer discloses an integrated circuit [see fig. 3B] comprising: a driver circuit [G1] having a reference terminal [terminal connected to C1] and a driver output [G1 output]; and a bias circuit [Q7, D1, D2 and Q8] coupled between a first terminal [A] and a second terminal [B], the bias circuit includes a first switch [Q7] coupled between the first terminal and a bias output [output from node between D1 and D2] and a second switch [Q8] coupled between the bias output and the second terminal, wherein each of the first switch and the second switch has a respective control terminal [control terminal Q7 and Q8] coupled to the driver output [via driver G1 when switches Q7 and Q8 are closed], or each of the first switch and the second switch has a respective diode [D1 and D2] or a diode-connected transistor.
Regarding claim 24, Kinzer discloses an integrated circuit [see fig. 3B] comprising: a bidirectional switch [Q5/Q6] coupled between a first drain terminal [drain terminal Q5/A], a second drain terminal [drain terminal Q6/B], and a common source [common source Q5/Q5]; a driver circuit [driver G1] having a reference terminal [terminal connected to C1] and a driver output [output G1], the reference terminal being electrically isolated from the common source [when output G1 low and Q5 and Q6 are off]; and a bias circuit [Q7, D1, D2 and Q8] coupled between the first terminal and the second terminal, the bias circuit includes a first switch [Q7] coupled between the first terminal and a bias output [output at node between D1 and D2] and a second switch [Q8] coupled between the bias output and the second terminal, wherein each of the first switch and the second switch has a respective control terminal [control terminal Q7 and Q8] coupled to the driver output, or each of the first switch and the second switch has a respective diode [D1 and D2] or a diode-connected transistor.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1- 2, 5, 7, 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer et al in view of Veliadis (US 2011/0121883).
Regarding claim 1, Kinzer discloses an integrated circuit [see fig. 3B] comprising: a driver circuit [G1] having a driver input [terminal C], a driver output [G1 output connected to gate Q5/Q6], a power terminal [terminal connected to node between D1 and D2], and a reference terminal [terminal connected to C1]; and a bias circuit [Q7, D1, D2 and Q8] having a first terminal [terminal connected to terminal A], a second terminal [terminal connected to terminal B], a bias control terminal [control terminal to terminals E and F], and a bias output [output at node between D1 and D2], the bias output coupled to the reference terminal, the bias circuit including a first transistor [Q7] coupled between the first terminal and the bias output and a second transistor [Q8] coupled between the bias output and the second terminal, the first transistor having a first control terminal [terminal E], and the second transistor having a second control terminal [terminal F], wherein the first control terminal and the second control terminal are coupled to the bias control terminal. Kinzer discloses not explicitly disclose the first and second control terminals receive a same control signal from the bias control terminal.
However, Veliadis discloses [see fig. 6] a first transistor [210] and second transistor [220] control terminals [G] receive a same control signal [VG] from the bias control terminal [230]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Kinzer by incorporating bias control terminal as taught in Veliadis in order to operate with low conduction losses, low switching losses, high frequency, and small physical size [par. 0030].
Regarding claim 2, Kinzer in view of Veliadis discloses [see fig. 3B] wherein the bias control terminal is electrically coupled to the driver output.
Regarding claim 5, Kinzer in view of Veliadis discloses [see fig. 3B] further comprising a bi-directional switch [Q5/Q6] coupled between the first terminal [A] and the second terminal [B], the bi-directional switch having a bi-directional switch control terminal [control terminal of Q5 and Q6] coupled to the driver output.
Regarding claim 7, Kinzer in view of Veliadis discloses [see fig. 3B] wherein the bi-directional switch includes: a single gate [gate to G1] structure coupled to the bi-directional switch control terminal; a first switch terminal [D terminal of Q5] coupled to the first terminal; and a second switch terminal [D terminal of Q6] coupled to the second terminal.
Regarding claim 8, Kinzer in view of Veliadis discloses [see fig. 3B] the bi-directional switch includes a third transistor [Q5] and a fourth transistor [Q6] serially connected between the first terminal and the second terminal; and the bi-directional switch control terminal is coupled to both a third control terminal [control terminal connected to G1] of the third transistor and a fourth control terminal of the fourth transistor.
Regarding claim 11, Kinzer in view of Veliadis discloses [see fig. 3B] wherein the bias circuit and the bi-directional switch are in a same semiconductor die [par. 0038].
Regarding claim 15, Kinzer in view of Veliadis discloses [see fig. 6 wherein the bias control terminal is coupled to the bias output.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kinzer et al. in view of Veliadis further in view of Ellis et al. (US 2024/0195295 and Ellis hereinafter).
Regarding claim 3, Kinzer in view of Veliadis discloses all the features with respect to claim 2 as indicated above. Kinzer in view of Veliadis does not disclose further comprising a resistor coupling the bias control terminal to the driver output.
However, Ellis discloses [see fig. 3] a resistor [R2] coupling a bias control terminal [Mboot control terminal] to a driver output [output coupled to gate M]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Kinzer in view of Veliadis by incorporating resistor as taught in Ellis in order to utilize high impedance elements that act to bias voltage in steady-state [par. 0054].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kinzer et al. in view of Veliadis further in view of Draxelmayr et al. (US 8558584 and Draxelmayr hereinafter).
Regarding claim 4, Kinzer in view of Veliadis discloses all the features with respect to claim 2 as indicated above. Kinzer in view of Veliadis does not disclose further comprising a voltage source coupled between the bias output of the bias circuit and the power terminal of the driver circuit.
However, Draxelmayr discloses [fig. 5] a voltage source [Vs1] coupled between a bias output [Vin] and power terminal [P1/P2] of a driver circuit [502]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Kinzer in view of Veliadis by incorporating a voltage source as taught in Draxelmayr in order to utilize the power supply voltage.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kinzer et al. in view of Veliadis further in view of Imam et al. (US 2019/0326280 and Imam hereinafter).
Regarding claim 6, Kinzer in view of Veliadis discloses all the features with respect to claim 5 as indicated above. Kinzer in view of Veliadis does not disclose wherein the bi-directional switch includes at least one high electron mobility transistor (HEMT).
However, Imam discloses [par. 0039] bi-directional switch includes at least one high electron mobility transistor (HEMT). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Kinzer in view of Veliadis by incorporating high electron mobility transistor (HEMT) in order to utilize a well-known, art-recognized functionally equivalent transistor device.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer et al. in view of Veliadis.
Regarding claims 9 and 10, Kinzer in view of Veliadis discloses all the features with respect to claim 8 as indicated above. Kinzer in view of Veliadis does not disclose wherein a first width ratio between the third transistor and the first transistor matches a second width ratio between the fourth transistor and the second transistor, wherein the first width ratio is greater than 100. One of ordinary skill in the art would have been motivated to have used the claimed range since such a dimension, absent any criticality (i.e. unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable dimension, where the general conditions of a claim are disclosed in the prior art, involves only routing skill in the art, In re Alter, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (i.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kinzer et al. in view of Ellis et al. (US 2024/0195295 and Ellis hereinafter).
Regarding claim 18, Kinzer discloses all the features with respect to claim 17 as indicated above. Kinzer does not disclose wherein the first control terminal and the second control terminal are electrically coupled to the driver output through a delay circuit.
However, Ellis discloses [see fig. 3, par. 0051] a control terminal [Mboot control terminal] is electrically coupled to the driver output through a delay circuit [RC]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Kinzer by incorporating delay circuit as taught in Ellis in order to utilize well known delay circuit [par. 0051].
Allowable Subject Matter
Claims 12-14 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed on 11/06/2025, with respect to the rejection of claims 1, 16 and 20 have been fully considered but they are not persuasive.
Regarding claim 16, applicant argues that Kinzer fails to disclose “a driver circuit having a power terminal, a reference terminal, and a driver output, the driver output coupled to the switch control terminal; and a bias circuit coupled between the first terminal and the second terminal, the bias circuit configurable to set a voltage of the reference terminal,”. Examiner respectfully disagrees.
Kinzer discloses [see fig. 3B] a driver circuit [G1] having a power terminal [power terminal G1 ], a reference terminal [terminal connected to C1] and a driver output [G1 output connected to gate Q5/Q6], the driver output coupled to the switch control terminal; and a bias circuit [Q7, D1, D2 and Q8] coupled between the first terminal [A] and the second terminal [B], the bias circuit having configurable to set a voltage [set a voltage at node between D1 and d2 through C1] of the reference terminal.
Regarding claim 1, applicant argues that Kinzer in view of Veliadis fails to disclose “a bias circuit having a first terminal, a second terminal, a bias control terminal, and a bias output, the bias output coupled to the reference terminal, the bias circuit including a first transistor coupled between the first terminal and the bias output and a second transistor coupled between the bias output and the second terminal, the first transistor having a first control terminal, and the second transistor having a second control terminal, wherein the first control terminal and the second control terminal are coupled to the bias control terminal to receive a same control signal from the bias control terminal.” Examiner respectfully disagrees.
Kinzer discloses [see fig. 3B] a bias control terminal [control terminal to terminals E and F], and a bias output [output at node between D1 and D2], the bias output coupled to the reference terminal, the bias circuit including a first transistor [Q7] coupled between the first terminal and the bias output and a second transistor [Q8] coupled between the bias output and the second terminal, the first transistor having a first control terminal [terminal E], and the second transistor having a second control terminal [terminal F], wherein the first control terminal and the second control terminal are coupled to the bias control terminal. Kinzer discloses not explicitly disclose the first and second control terminals receive a same control signal from the bias control terminal.
However, Veliadis discloses [see fig. 6] a first transistor [210] and second transistor [220] control terminals [G] receive a same control signal [VG] from the bias control terminal [230]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Kinzer by incorporating bias control terminal as taught in Veliadis in order to operate with low conduction losses, low switching losses, high frequency, and small physical size [par. 0030].
Regarding claim 20, applicant argues that Kinzer fails to disclose “a bias circuit including a first circuit coupled between the first terminal and the reference terminal and a second circuit coupled between the reference terminal and the second terminal, wherein the first circuit and the second circuit are configurable to connect the reference terminal to the first terminal responsive to the first terminal having a lower voltage level than the second terminal.” Examiner respectfully disagrees.
Kinzer discloses [see fig. 3B]a bias circuit [Q7, D1, D2 and Q8] including a first circuit [Q7and D1] coupled between the first terminal and the reference terminal and a second circuit [Q8 and D2] coupled between the reference terminal and the second terminal, wherein the first circuit and the second circuit are configurable to connect the reference terminal to the first terminal responsive to the first terminal having a lower voltage level than the second terminal [par. 0042-0055].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to METASEBIA T RETEBO whose telephone number is (571)272-9299. The examiner can normally be reached M - F 8:30 - 5.
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2842