DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species A1 in the reply filed on 08/07/2026 is acknowledged.
Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/07/2026.
Applicant’s cancellation of claims 14-20 and added new claims 21-26 in the reply filed on 08/07/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement filed 05/14/2024 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered,
There are no copies for Cite No. A43, A44, A46, A47 as cited.
The information disclosure statement filed 05/14/2024 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because there are no English translations for Cite No. A40, A41, A48, A49, A50 as cited. See 37 CFR 1.98(a)(3)(ii). It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Claim Objections
Claim 1 is objected to because of the following informalities:
Regarding claim 1, line 13 – “second error difference” needs to be changed to “second error difference signal”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-13 and 21-26 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for two or more data circuits and two or more pilot circuits, does not reasonably provide enablement for one or more data circuits and one or more pilot circuits as claimed. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the invention commensurate in scope with these claims.
Regarding claim 1, the claimed limitation of “a first error difference signal corresponding to the one or more data circuits and a second error difference corresponding to the one or more pilot circuits” fails the scope of enablement requirement (emphasis added). As can be seen from Applicant’s disclosure - paragraph [0042], Figure 2, and further claimed in claims 8 and 13, the claimed invention requires two or more data circuits to produce a first error difference signal. Likewise, the claimed invention requires two or more pilot circuits to produce a second error difference signal. Therefore, just one data circuit (i.e. reads on the claimed language of “one or more”) and just one pilot circuit (i.e. reads on the claimed language of “one or more”) cannot cause the desired result such that a person of ordinary skill in the art could make and use the invention commensurate in scope with these claims.
Regarding claim 21, the claimed limitations of “one or more data circuits configured to process the in-phase signal and the quadrature signal for the data component using an early time offset and a late time offset to generate a data error difference signal” and “one or more pilot circuits configured to process the in-phase signal and the quadrature signal for the pilot component using an early time offset and a late time offset to generate a pilot error difference signal” fail the scope of enablement requirement (emphasis added). As can be seen from Applicant’s disclosure - paragraph [0042], Figure 2, and further claimed in claims 8 and 13, the claimed invention requires two or more data circuits to produce a first error difference signal. Likewise, the claimed invention requires two or more pilot circuits to produce a second error difference signal. Therefore, just one data circuit (i.e. reads on the claimed language of “one or more”) and just one pilot circuit (i.e. reads on the claimed language of “one or more”) cannot cause the desired result such that a person of ordinary skill in the art could make and use the invention commensurate in scope with these claims.
Regarding claim 24, the claimed limitations of “processing, by one or more data circuits of the device, the in-phase signal and the quadrature signal for a data signal component using an early time offset and a late time offset to generate a data error difference signal” and “processing, by one or more pilot circuits of the device, the in-phase signal and the quadrature signal for a pilot signal component using an early time offset and a late time offset to generate a pilot error difference signal” fail the scope of enablement requirement (emphasis added). As can be seen from Applicant’s disclosure - paragraph [0042], Figure 2, and further claimed in claims 8 and 13, the claimed invention requires two or more data circuits to produce a first error difference signal. Likewise, the claimed invention requires two or more pilot circuits to produce a second error difference signal. Therefore, just one data circuit (i.e. reads on the claimed language of “one or more”) and just one pilot circuit (i.e. reads on the claimed language of “one or more”) cannot cause the desired result such that a person of ordinary skill in the art could make and use the invention commensurate in scope with these claims.
Other claims are also rejected based on their dependency of the defected parent claims.
Allowable Subject Matter
Claims 1-13 and 21-26 are allowed over prior art. However, 35 USC 112(a) rejections must be overcome.
Conclusion
The cited prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2025/0291064 discloses a method of satellite signal acquisition includes generating a pilot correlation output based on a pilot signal of a received signal from the satellite; generating a data correlation output based on a data signal of the received signal from the satellite; integrating the pilot correlation output to generate an integrated pilot output; integrating the data correlation output to generate an integrated data output; differential combining of the integrated pilot output; differential combining of the integrated data output; summing and applying a coherent integrator to generate an output signal; determining a phase of the output signal; and determining a Doppler of the output signal.
US 2023/0213662 discloses a global navigation satellite system (GNSS) receiver for improving accuracy of a GNSS position estimation using a sigma-delta based fractional interpolation in a delay-locked loop. The GNSS receiver includes a correlator, a code phase discriminator, a first loop filter, a code numerically controlled oscillator, and a sigma-delta modulator. The correlator correlates a GNSS C/A signal received from a satellite with a locally generated GNSS C/A code by multiplying the locally generated GNSS C/A code with incoming data samples. The code phase discriminator determines a delay between the locally generated GNSS C/A code and the GNSS C/A signal received from the satellite. The first loop filter averages the delay measured by the code phase discriminator. The code numerically controlled oscillator generates the local GNSS C/A code based on a unique CA code that corresponds to the satellite. The sigma-delta modulator imparts a fractional delay to the locally generated GNSS C/A code based on an output of the first loop filter.
US 10,976,442 discloses a method and apparatus are provided for processing navigation signals with improved stability in a multi-frequency, multi-system environment. Satellite signals, which are transmitted by a plurality of satellites from a plurality of different global navigation satellite systems, are received on a common radio path and processed in separate digital satellite channels, with each of the separate digital satellite channels corresponding to a respective satellite signal. A common quartz-locked-loop (QLL) discriminator signal is generated based on correlation signals from each of the separate digital satellite channels. Based on the common QLL discriminator signal, guiding signals are generated, with each of the guiding signals corresponding to a respective one of the separate digital satellite channels, for reducing phase-related tracking errors in the respective satellite signal processed in its corresponding digital satellite channel.
US 10,649,095 discloses a method for joint data-pilot tracking of navigation signal, including: multiplying a digital intermediate frequency signal with a local carrier to accomplish carrier removal; multiplying a signal after the carrier removal with a data baseband signal and a pilot baseband signal respectively to accomplish code removal; processing a signal after the code removal with integration-and-dump to obtain a coherent integration result of each branch; using the coherent integration results to accomplish data-bit flip detection and calculation of probability-weighting factor; acquiring a data-pilot joint carrier tuning-amount, and tuning the carrier numerically controlled oscillator by the carrier tuning-amount to realize data-pilot joint signal carrier tracking; and acquiring a data-pilot joint code tuning-amount, and tuning the code numerically controlled oscillator to realize baseband signal tracking.
US 9,385,767 discloses a correction phase locked loop (CPLL), including a signal processing unit that receives a digitized input signal from a satellite, the signal processing unit comprising (a) a primary correlator and primary discriminator, connected in series and generating a main error signal Z1 from the digitized input signal; (b) a correction correlator and a correction discriminator connected in series and generating a correction signal Z2; and (c) an adder for adding the main error signal Z1 and the correction signal Z2 to produce a common error signal Z. A loop filter filters the common error signal Z to produce a corrected error signal that is used for frequency-phase control of a Numerical Control Oscillator (NCO). The NCO generates two mutually orthogonal output reference signals whose phase is substantially free of multipath errors.
US 2015/0097729 discloses a GNSS receiver to track low power GNSS satellite signals. The GNSS receiver includes a frequency locked loop (FLL) that measures a current doppler frequency of the satellite signal. A delay locked loop (DLL) measures a current code phase delay of the satellite signal. A current operating point corresponds to the current doppler frequency and the current code phase delay of the satellite signal. A grid monitor receives the satellite signal and the current operating point, and measures a satellite signal strength at a plurality of predefined offset points from the current operating point. The FLL and the DLL are centered at the current operating point. A peak detector is coupled to the grid monitor and processes the satellite signal strengths at the plurality of predefined offset points and re-centers the FLL and the DLL to a predefined offset point with the satellite signal strength above a predefined threshold.
US 2014/0362955 discloses a transceiver includes an input node to receive an input signal having in-phase (I) data and quadrature (Q) data, the input signal including several data samples. A correlation module determines an autocorrelation of the in-phase data, an autocorrelation of the quadrature data, a difference between the autocorrelation of the in-phase data and the autocorrelation of the quadrature data, and a cross correlation between the in-phase data and the quadrature data. An averaging module determines an average of the difference between the autocorrelation of the in-phase data and the autocorrelation of the quadrature data, and an average of the cross correlation between the in-phase data and the quadrature data, in which the averages are determined over a specified number of data samples. A compensation module, based on the average difference between the autocorrelation of the in-phase data and the autocorrelation of the quadrature data, and the average cross correlation between the in-phase data and the quadrature data, determines compensated in-phase data and quadrature data having reduced IQ mismatch.
US 7,706,431 discloses a system architecture for a receiver to process multiple signals on a common carrier frequency from a satellite. The receiver is arranged such that the receiver receives input data transmitted from the satellite. A pilot signal is tracked from the input data using a correlation channel, and a data signal is tracked from the input data using a data code generator operatively connected to the correlation channel. In one embodiment of the invention, the data signal generator creates replica code for the data signal. In another embodiment of the invention, the system can switch between the data signal generator and pilot signal generator based upon the signal-to-noise ratio of the incoming signal.
JP 2001507788 discloses a technique for processing signals, which is particularly applied to receiver and range finding applications for radio frequency signals having a pseudo-random noise (PRN) code modulated on a carrier. These are applied in global positioning system (GPS or GLONASS) receivers. Both the receiver DLL code and the PLL carrier loop include loop elements that detect errors in the main loop caused by the presence of multipath signals. The main loop is continually adjusted by this detected error, which causes the loop to more accurately track and minimize the effects of multipath signals. As a result, more accurate distance measurement can be performed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUONG P NGUYEN whose telephone number is (571)272-3445. The examiner can normally be reached Mon-Fri, 10:00-10:00 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JACK KEITH can be reached at (571) 272-6878. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUONG P NGUYEN/Primary Examiner, Art Unit 3646
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