DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 – 7 and 14 – 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claims are directed to software per se.
Claims 1 – 7 and 14 – 20 are directed towards “an apparatus” comprising “a first interrupt priority register” (claim 1), “a second interrupt priority register” (claim 1), “means for determining a first priority level…” (claim 14), and “means for determining a second priority level…” (claim 14). Applicant has disclosed that the “apparatuses and techniques” of the invention described and illustrated as various “elements” and that the “elements” may be implemented using hardware, software, or combinations thereof” (Originally Filed Specification; Paragraph [0020]). Applicant has also disclosed that the various operations and methods of the invention “may be performed by any suitable means capable of performing the corresponding functions” and that the means “may include various hardware and/or software component(s)…” (Originally Filed Specification; Paragraph [0085]). Therefore, it is reasonable to interpret the elements of the claimed apparatuses (claims 1 – 7 and 14 – 20) as being directed to software per se. Software per se does not fall within one of the four categories of invention and are thus not statutory. Therefore, claims 1 – 7 and 14 – 20 are not statutory and are not patent eligible.
Allowable Subject Matter
Claims 1 – 7 and 14 – 20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 101 set forth in this Office action.
Claims 8 – 13 are allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1 – 7 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 101 set forth in this Office action because the prior art of record fails to teach or suggest alone or in combination a first interrupt priority register mapping a first portion of each nested interrupt identification (ID) value of a set of nested interrupt ID values to a first set of priority levels, each first portion corresponding to one of the first set of priority levels; and a second interrupt priority register mapping a second portion of each nested interrupt ID value of the set of nested interrupt ID values to a second set of priority levels, such that each nested interrupt ID value corresponds to two priority levels, the set of nested interrupt ID values corresponding to merged interrupt sources coupled to a single interrupt line, as required by independent claim 1, in combination with the other claimed limitations (emphasis added). US Patent No. 8,560,750 (hereinafter Sarkar) teaches an interrupt processing system which stores interrupt priorities (Sarkar; Figure 4 Item 410) and uses the interrupt priority list to process interrupt requests (Sarkar; Col 7 Line 48 – Col 8 Line 3). However, Sarkar does not teach the details of the first interrupt priority register combined with the details of the second interrupt priority register and nested interrupt ID values required by independent claim 1. US Patent Application Publication No. 2005/0021894 (hereinafter Traynor) teaches an interrupt processing system which maps interrupt sources to interrupt inputs and changing the priority of an interrupt source through control bits (Traynor; Paragraphs [0029] and [0030]). However, Traynor does not teach the details of the first interrupt priority register combined with the details of the second interrupt priority register and nested interrupt ID values required by independent claim 1.
Claims 2 – 7 would also be allowable because of their dependence, either directly or indirectly, upon allowable independent claim 1.
Claims 8 – 13 are allowable because the prior art of record fails to teach or suggest alone or in combination determining a first priority level for each nested interrupt ID value of a set of nested interrupt ID values from a first interrupt priority register mapping a first portion of each nested interrupt ID value to the first priority level, which is from a first set of priority levels; and determining a second priority level for each nested interrupt ID value of the set of nested interrupt ID values from a second interrupt priority register mapping a second portion of each nested interrupt ID value to the second priority level, which is from a second set of priority levels, the set of nested interrupt ID values corresponding to merged interrupt sources coupled to a single interrupt line, as required by independent claim 8, in combination with the other claimed limitations (emphasis added). US Patent No. 8,560,750 (hereinafter Sarkar) teaches an interrupt processing system which stores interrupt priorities (Sarkar; Figure 4 Item 410) and uses the interrupt priority list to process interrupt requests (Sarkar; Col 7 Line 48 – Col 8 Line 3). However, Sarkar does not teach the details of determining first and second priority levels for nested interrupt ID values from first and second priority registers required by independent claim 8. US Patent Application Publication No. 2005/0021894 (hereinafter Traynor) teaches an interrupt processing system which maps interrupt sources to interrupt inputs and changing the priority of an interrupt source through control bits (Traynor; Paragraphs [0029] and [0030]). However, Traynor does not teach the details of determining first and second priority levels for nested interrupt ID values from first and second priority registers required by independent claim 8.
Claims 9 – 13 are also allowable because of their dependence, either directly or indirectly, upon allowable independent claim 8.
Claims 14 – 20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 101 set forth in this Office action because the prior art of record fails to teach or suggest alone or in combination means for determining a first priority level for each nested interrupt ID value of a set of nested interrupt ID values from a first interrupt priority register mapping a first portion of each nested interrupt ID value to the first priority level, which is from a first set of priority levels; and means for determining a second priority level for each nested interrupt ID value of the set of nested interrupt ID values from a second interrupt priority register mapping a second portion of each nested interrupt ID value to the second priority level, which is from a second set of priority levels, the set of nested interrupt ID values corresponding to merged interrupt sources coupled to a single interrupt line, as required by independent claim 14, in combination with the other claimed limitations (emphasis added). US Patent No. 8,560,750 (hereinafter Sarkar) teaches an interrupt processing system which stores interrupt priorities (Sarkar; Figure 4 Item 410) and uses the interrupt priority list to process interrupt requests (Sarkar; Col 7 Line 48 – Col 8 Line 3). However, Sarkar does not teach the details of determining first and second priority levels for nested interrupt ID values from first and second priority registers required by independent claim 14. US Patent Application Publication No. 2005/0021894 (hereinafter Traynor) teaches an interrupt processing system which maps interrupt sources to interrupt inputs and changing the priority of an interrupt source through control bits (Traynor; Paragraphs [0029] and [0030]). However, Traynor does not teach the details of determining first and second priority levels for nested interrupt ID values from first and second priority registers required by independent claim 14.
Claims 15 – 20 would also be allowable because of their dependence, either directly or indirectly, upon allowable independent claim 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RICHARD B FRANKLIN/ Examiner, Art Unit 2181
Prosecution Insights