Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 15-20 are withdrawn from consideration as directed to non-elected invention. Claims 1-14 are being examined.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-14 in the reply filed on 9/3/26 is acknowledged.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9/3/26.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 8-13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub. 2024/0370781 to Padmanabha Iyer et al. (hereafter Padmanabha Iyer).
As to claim 12, Padmanabha Iyer teaches the invention as claimed including a method comprising:
receiving, via an input of at least one circuit, a first amount of data to be processed with at least one model in the at least one circuit [receiving task requests to perform tasks by scheduling the requests with ML model(s), paragraphs 33, 49 and 78];
generating additional data based on configuration data indicating that when input data of the first amount is to be processed with the at least one model, the input data should be supplemented with additional data to yield a second amount of data to be processed [batching of requests and dynamically padding the inputs to the length of the largest input in a batch, paragraphs 12, 28 and 54-56];
supplementing the first amount of data with the additional data to yield aggregated data that has the second amount of data, the second amount of data being larger than the first amount of data processed [batching of requests and dynamically padding the inputs to yield the length of the largest input in a batch, paragraphs 12, 28 and 54-56; Fig. 8 and corresponding text]; and
processing the aggregated data with the at least one model, the aggregated data comprising the first amount of data and the additional data [processing of padded batches with and without scheduling optimization, paragraph 56].
As to claim 13, Padmanabha Iyer teaches the invention as claimed including further comprising processing, with the at least one model, the aggregated data in a number of batches identified by the configuration data [batching of requests and dynamically padding the inputs to yield the length of the largest input in a batch for processing, paragraphs 12, 28 and 54-56; Fig. 8 and corresponding text; computing system being configured by computer-executable instruction to perform the functions, paragraph 68].
As to claims 1-2, Padmanabha Iyer teaches the method for adjusting batch and/or workload size for model processing in claims 12-13, therefore Padmanabha Iyer teaches the apparatus for implementing the method. Furthermore, Padmanabha Iyer teaches a computing system with processor and input [abstract; Fig. 9 and corresponding text].
As to claim 3, Padmanabha Iyer teaches the invention as claimed including wherein processing the aggregated data in the number of batches identified by the configuration data comprises, based on the configuration data, dividing the aggregated data into the number of batches, the number of batches each comprising an amount of data identified by the configuration [batches of requests with minimal padding, paragraphs 12, 28 and 54-56; Fig. 8 and corresponding text; computing system being configured by computer-executable instruction to perform the functions, paragraph 68.
As to claim 4, Padmanabha Iyer teaches the invention as claimed including wherein dividing the aggregated data into the number of batches comprises dividing the aggregated data into two batches, each batch having a different amount of data [Request IDs 1-4 which would have been group in one batch without input-aware scheduling are divided into two batches (i.e. length 32 and 128) having different amount of data, Fig. 8 and corresponding text].
As to claim 8, Padmanabha Iyer teaches the invention as claimed including wherein the configuration data is associated with the at least one model and with the at least one circuit with which the at least one model is to execute [batching of requests and dynamically padding the inputs to yield the length of the largest input in a batch for processing by a model, abstract; paragraphs 12, 28 and 54-56; Fig. 8 and corresponding text; computing system being configured by computer-executable instruction to perform the functions, paragraph 68].
As to claim 9, Padmanabha Iyer teaches the invention as claimed including wherein the configuration data indicates, for each amount of data of a plurality of amounts of data that may be received as input to be processed with the at least one model: a number of batches in which to process that amount of data with the at least one model, and/or a larger amount of data to process with the at least one model when that amount of data is received [batching of requests and dynamically padding the inputs to yield the length of the largest input in a batch for processing by a model, abstract; paragraphs 12, 28 and 54-56; Fig. 8 and corresponding text; computing system being configured by computer-executable instruction to perform the functions, paragraph 68].
As to claim 10, Padmanabha Iyer teaches the invention as claimed including wherein in a case that the configuration data indicates that, for an amount of data, a larger amount of data is to be processed, the configuration data further indicates a number of batches in which to process that larger amount of data [batching of requests and dynamically padding the inputs to yield the length of the largest input in a batch for processing by a model, abstract; paragraphs 12, 28 and 54-56; Fig. 8 and corresponding text; computing system being configured by computer-executable instruction to perform the functions, paragraph 68].
As to claim 11, Padmanabha Iyer teaches the invention as claimed including wherein the at least one circuit comprises at least one execution circuit to execute instructions and at least one storage having encoded thereon executable instructions that, when executed by the at least one execution circuit, causes the at least one execution circuit to perform the generating based on the configuration data and the processing the aggregated data [batching of requests and dynamically padding the inputs to yield the length of the largest input in a batch for processing by a model, abstract; paragraphs 12, 28 and 54-56; Fig. 8 and corresponding text; computing system being configured by computer-executable instruction to perform the functions, paragraph 68].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Padmanabha Iyer as applied to claim 1 above.
As to claim 5, Padmanabha Iyer does not specifically teach wherein generating the additional data comprises generating data matching a pattern. However, it is well known in the art to use NULL bytes (i.e. 0x00) or other fixed value as padding filler data. It would have been obvious to one of ordinary skill in the art before the effective filing date to have implement various fixed pattern data filler or dummy data as a matter of design choice.
Claim(s) 6-7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Padmanabha Iyer as applied to claims 1 and 12 above, further in view of “Observing and Preventing Leakage in MapReduce” to Ohrimenko et al. (hereafter Ohrimenko).
As to claim 14, Padmanabha Iyer does not specifically storing an identification of the additional data; and discarding results corresponding to the identification. However, Padmanabha Iyer disclosed that padding tokens in a batch is wasted computation [paragraph 54, lines 10-13; paragraph 55, lines 1-3]. Furthermore, Ohrimenko teaches the implementation fo batching and padding in data communication in which dummy data in padded output are removed or discarded [section 6. Shuffle-in-the-Middle Solution and section 7.1 Overview, pp. 1577-1578]. It would have been obvious to one of ordinary skill in the art before the effective filing date to have modify Padmanabha Iyer with Ohrimenko to conserve resources by discarding results of wasted computation as being considered by Ohrimenko.
As to claims 6-7, these claims are rejected for the same reason as claim 14 above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QING YUAN WU whose telephone number is (571)272-3776. The examiner can normally be reached M-F 9AM-6PM EST.
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/QING YUAN WU/Primary Examiner, Art Unit 2199
