DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-10 and 16-20 in the reply filed on 08/03/2026 is acknowledged. Claims 11-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, the metes and bounds of the claimed invention are vague and ill-defined as a result of uncertainty in the different boundaries, “the second interconnect level” in line 1. The claim is indefinite because there is insufficient antecedent basis for this limitation in the claim. For purposes of evaluating the prior art, the examiner is unable to ascertain the difference between the second interconnect level and the second metal interconnect layer. Appropriate clarification and/or correction are/is required within the metes and bounds of the claimed invention.
As there is a great deal of confusion and uncertainty as to the proper interpretation of the limitation of claim 7, it would not be proper for the examiner to reject such a claim on the basis of the prior art. See MPEP §706.03.II (second).
Claim 8 is rejected because it is directly dependent on claim 7.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. US 7,919,802.
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Lin et al. US 7,919,802
Regarding claim 1, Lin et al. in Fig. 5 and col. 4, lines 15-42 disclose an integrated circuit (IC), comprising:
a metal-insulator-metal capacitor (MIMCAP) 70 in a dielectric layer 58 over a semiconductor substrate 41, the MIMCAP having a top plate 66 and a bottom plate 62 having a lateral perimeter defining a bottom plate lateral area (annotated above);
a first metal interconnect layer 74 over the MIMCAP 70 connected to the top plate 66; and
a second metal interconnect layer 53 below the MIMCAP 70 touching the bottom plate 62, a contact area (annotated above) between the second metal interconnect layer 53 and the bottom plate 62 being less than the bottom plate lateral area (annotated above).
Claim(s) 1, 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. US 11,245,000.
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Huang et al. US 11,245,000
Regarding claim 1, Huang et al. in Fig. 4 and col. 3, line 30-col. 6, line 3 disclose an integrated circuit (IC), comprising:
a metal-insulator-metal capacitor (MIMCAP) 2 in a dielectric layer 106 over a semiconductor substrate 100, the MIMCAP 2 having a top plate TE and a bottom plate BE having a lateral perimeter defining a bottom plate lateral area (annotated above);
a first metal interconnect layer C2 over the MIMCAP 2 connected to the top plate TE; and
a second metal interconnect layer 53 below the MIMCAP 70 touching the bottom plate 62, a contact area (annotated above) between the second metal interconnect layer 53 and the bottom plate 62 being less than the bottom plate lateral area (annotated above).
Regarding claim 3, Huang et al. in Fig. 4 and col. 3, line 30-col. 6, line 3 disclose the IC of claim 1 wherein the MIMCAP 70 includes an oxide-nitride-oxide (ONO) dielectric layer CD between the top plate TE and the bottom plate BE col. 4, lines 27-30.
Claim(s) 1, 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsue et al. US 6,504,205.
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Hsue et al. US 6,504,205
Regarding claim 1, Hsue et al. in Fig. 2J and col. 3, line 12-col. 4, line 41 disclose an integrated circuit (IC), comprising:
a metal-insulator-metal capacitor (MIMCAP) 140 in a dielectric layer 110 over a semiconductor substrate col. 3, lines 12-15, the MIMCAP 140 having a top plate 118 and a bottom plate 114 having a lateral perimeter defining a bottom plate lateral area (annotated above);
a first metal interconnect layer 130a over the MIMCAP 140 connected to the top plate 118; and
a second metal interconnect layer 104a below the MIMCAP 140 touching the bottom plate 114, a contact area (annotated above) between the second metal interconnect layer 104a and the bottom plate 114 being less than the bottom plate lateral area (annotated above).
Regarding claim 9, Hsue et al. in Fig. 2J and col. 3, line 12-col. 4, line 41 disclose the IC of claim 1 wherein the first and second metal interconnect layers 130a, 104a are copper interconnect layers col. 3, lines 23-26.
Claim(s) 1, 5-6 and 16-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tu et al. US 2010/0065944.
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Tu et al. US 2010/0065944
Regarding claim 1, Tu et al. in Fig. 6 and [0016]-[0030] disclose an integrated circuit (IC), comprising:
a metal-insulator-metal capacitor (MIMCAP) in a dielectric layer 160a, 160b over a semiconductor substrate [0018], the MIMCAP (e.g. Cap1, Cap2) having a top plate (e.g. top electrode of MIMCAP) and a bottom plate (e.g. bottom electrode of MIMCAP) having a lateral perimeter defining a bottom plate lateral area (annotated above);
a first metal interconnect layer 170/180 over the MIMCAP connected to the top plate; and a second metal interconnect layer 195a below the MIMCAP touching the bottom plate (e.g. bottom electrode of Cap1, Cap2) , a contact area between the second metal interconnect layer 195a and the bottom plate (e.g. bottom electrode of Cap1, Cap2) being less than the bottom plate lateral area (annotated above).
Regarding claim 5, Tu et al. in Fig. 6 and [0016]-[0030] disclose the IC of claim 1 wherein the MIMCAP is one of a plurality of MIMCAPs arranged in linear arrays, the MIMCAPs of each linear array connected to one of a corresponding plurality of traces in the second interconnect layer 195a.
Regarding claim 6, Tu et al. in Fig. 6 and [0016]-[0030] disclose the IC of claim 5 but do not expressly disclose wherein the plurality of traces have a first width inside the lateral perimeters of the bottom plates and a second greater width outside the lateral perimeters of the bottom plates.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 16, Tu et al. in Fig. 6 and [0016]-[0030] disclose an integrated circuit device, comprising:
a plurality of layers 160a, 160b formed over a semiconductor substrate [0018] and including a lower metal layer, an upper metal layer, and at least one dielectric layer interposing the lower and upper metal layers; and
a plurality of metal plates 195a, 195b [0028] each having a bottom surface, wherein a contact area between each metal plate 195 and the lower metal layer 160: extends from a first side of a perimeter of that metal plate 195 to an opposite side of the perimeter; and is less than a bottom surface area of that metal plate 195 (annotated above).
Regarding claim 17, Tu et al. in Fig. 6 and [0016]-[0030] disclose the integrated circuit device of claim 16 wherein each metal plate 195a, 195b is a bottom plate of a corresponding one of a plurality of trench capacitors 160a, 160b.
Regarding claim 18, Tu et al. in Fig. 6 and [0016]-[0030] disclose the integrated circuit device of claim 17 wherein the lower metal layer and the metal plates form a first terminal of an array capacitor [0019].
Regarding claim 19, Tu et al. in Fig. 6 and [0016]-[0030] disclose the integrated circuit device of claim 17 further comprising a transistor [0016] formed at least partially in the semiconductor substrate and interconnected with at least one of the trench capacitors.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsue et al. US 6,504,205 as applied to claim 1 above, and further in view of Hu US 2011/0057292.
Regarding claim 2, Hsue et al. in Fig. 2J and col. 3, line 12-col. 4, line 41 disclose the IC of claim 1 wherein the second metal interconnect layer 104a includes a metal trace (e.g. a wire col. 3, lines 25-27) touching the bottom plate 114 and having a path and a linewidth less than a lateral diameter of the bottom plate at an intersection of the path and the lateral perimeter (annotated above).
Hsue et al. does not expressly disclose a lateral diameter. Hu in Fig. 6 and [0022] teach a MIM capacitor 100 Fig. 11 can have a geometry including but not limited to a square or a circular shape.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a MIM capacitor with a lateral diameter of the bottom plate, as the court has held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is prima facie obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsue et al. US 6,504,205 as applied to claim 1 above, and further in view of Hsue et al. US 6,410,386.
Regarding claim 4, Hsue et al. 205 in Fig. 2J and col. 3, line 12-col. 4, line 41 disclose the IC of claim 1 wherein the first interconnect layer is connected to the MIMCAP by a via and the second metal interconnect layer includes a metal trace that touches the bottom plate and has a linewidth about equal to a width of the via.
Hsue et al. 386 in Fig. 2L and col. 5, lines 7-29 teach an IC including a first interconnect layer 140 connected to a MIM capacitor 132 by a via 140 and a second metal interconnect 124a includes a metal trace 124a col. 3, line 52and has a linewidth about equal to a width of the via 140. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first interconnect layer is connected to the MIMCAP by a via and the second metal interconnect layer includes a metal trace that touches the bottom plate and has a linewidth about equal to a width of the via, as the court has held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is prima facie obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsue et al. US 6,504,205 as applied to claim 1 above, and further in view of Huang et al. US 2018/0061752.
Regarding claim 10, Hsue et al. in Fig. 2J and col. 3, line 12-col. 4, line 41 disclose the IC of claim 1 including numerous devices formed in and on a semiconductor substrate but do not expressly disclose the IC of claim 1 further comprising a transistor extending into the semiconductor substrate and interconnected with the MIMCAP.
Huang et al. in Fig. 1 and [0016]-[0017] teach an MOS transistor 14 disposed on a substrate 12, including a gate structure 16 on the substrate and a source/drain region 20 in the substrate and interconnected with a MIM capacitor. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a transistor extending into the semiconductor substrate and interconnected with the MIMCAP, as the court has held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is prima facie obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tu et al. US 2010/0065944.
Regarding claim 20, Tu et al. in Fig. 6 and [0016]-[0030] disclose the integrated circuit device of claim 16 but do not expressly disclose wherein the contact area between each metal plate and the lower metal layer is at least 20% less than the bottom surface area of that metal plate.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Sonya McCall-Shepard/Primary Examiner, Art Unit 2898
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