DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 21 is rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Sharma (US 20210218375 A1). Sharma teaches (in Fig. 1) a transmit circuit (105) having a transmit input (IP), a first transmit output (105 output coupled to CPAC input), and a second transmit output (105 output coupled to PAC1) input; a first amplifier (CPAC) having a first amplifier input (CPAC input) and a first amplifier output (CPAC output), the first amplifier input coupled to the first transmit output (top output of 105 is coupled to CPAC input); a second amplifier (PAC1) having a second amplifier input (input of PAC1) and a second amplifier output (output of PAC1), the second amplifier input coupled to the second transmit output (bottom output of 105 is coupled to CPAC input), and the first and second amplifiers having different power levels at saturation (the second amplifier has a higher supply voltage per claim 9, therefore has higher output power level at all times); and a quadrature hybrid combiner (110) coupled between the first and second amplifier outputs and a combiner output (labeled as 4 in Fig. 5).
Claims 22-25 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liu (A 44–64-GHz mm Wave Broadband Linear Doherty PA in Silicon With Quadrature Hybrid Combiner and Non-Foster Impedance Tuner).
Regarding claim 22, as best understood, in Fig. 1(b) Liu teaches that the quadrature hybrid combiner includes a quadrature phase terminal (P2), an in phase terminal (P3), a reference terminal (P1), and an isolation terminal (P4), the in phase terminal coupled to the first amplifier output(P3 is connected to Class AB CR PA output), the quadrature phase terminal coupled to the second amplifier output (P2 is connected to Class C PK PA output), the reference terminal coupled to a combiner output (P1 is output port per section B. (1)), and the isolation terminal (P4) coupled to a direct current (DC) voltage source (source of V4).
Regarding claim 23, as best understood, Liu teaches in Fig. 5(a) that the quadrature hybrid combiner includes a first coil electrically coupled between the reference terminal and the quadrature phase terminal (coil between P1 and P2) and a second coil electrically coupled between the in-phase terminal and the isolation terminal (coil between P3 and P4), the first coil being magnetically coupled to the second coil (the coils are part of a 1:1 transformer per section E paragraph 2, therefore they are magnetically coupled).
Regarding claim 24, as best understood, Liu teaches in Fig. 5(a), a first capacitor coupled between the in phase terminal and a DC terminal (capacitor between P3 and ground); a second capacitor coupled between the quadrature phase terminal and the DC terminal (capacitor between P2 and ground); a third capacitor coupled between the reference terminal and the DC terminal (capacitor between P1 and ground); a fourth capacitor coupled between the isolation terminal and the DC terminal (capacitor between P4 and ground); a fifth capacitor coupled between the quadrature phase terminal and the isolation terminal (capacitor between P2 and P4); and a sixth capacitor coupled between the in-phase terminal and the reference terminal (capacitor between P1 and P3).
Regarding claim 25, as best understood, Liu teaches in Fig. 5(a), further labeled in Figure I of the present office action above, that the first coil has a first center tap terminal (Center tap 1), the second coil has a second center tap terminal (Center tap 2), and the apparatus further comprises: a first capacitor coupled between the in-phase terminal and a DC terminal (capacitor between P3 and ground); a second capacitor coupled between the quadrature phase terminal and the DC terminal (capacitor between P2 and ground); a third capacitor coupled between the reference terminal and the DC terminal (capacitor between P1 and ground); a fourth capacitor coupled between the isolation terminal and the DC terminal (capacitor between P4 and ground); a fifth capacitor coupled between the first center tap terminal and the DC terminal (capacitor between Center tap 1 ground); a seventh capacitor coupled between the quadrature phase terminal and the isolation terminal (capacitor between P2 and P4); an eighth capacitor coupled between the in-phase terminal and the reference terminal (capacitor between P3 and P1); and a ninth capacitor coupled between the first and second center tap terminals (capacitor between Center tap 1 and Center tap 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-14 and 16 and 26 are rejected under 35 U.S.C. 103 as being obvious over Liu (A 44–64-GHz mmWave Broadband Linear Doherty PA in Silicon With Quadrature Hybrid Combiner and Non-Foster Impedance Tuner), in view of Asbeck (WO 2021021934 A1).
Regarding claim 1, Liu teaches, in Fig. 1 (b), a first amplifier (Class AB CR PA) having a first amplifier output (output of Class AB CR PA) and configured to provide a first signal (I3 and V3) having a first power level at the first amplifier output; a second amplifier (Class C PK PA) having a second amplifier output (output of Class C PK PA) and configured to provide a second signal (I2 and V2) having a second power level at the second amplifier output. Liu also teaches a combiner circuit (Fig. 1. (b)) having a quadrature phase terminal (P2), an in phase terminal (P3), a reference terminal (P1), and an isolation terminal (P4), the in phase terminal coupled to the first amplifier output (P3 is connected to Class AB CR PA output), the quadrature phase terminal coupled to the second amplifier output (P2 is connected to Class C PK PA output), the reference terminal coupled to a combiner output (P1 is output port per section B. (1)), and the isolation terminal (P4) coupled to a direct current (DC) voltage source (source of V4).
Liu does not teach that the second power level being higher than the first power level.
Asbeck teaches the second power level being higher than the first power level (claim 9).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to use the second power level be higher than the first as taught by Asbeck with the amplifiers taught by Liu to match the voltage swings of the main and auxiliary amplifiers at maximum power.
Regarding claim 2, Liu teaches that the combiner circuit includes a quadrature hybrid combiner (Fig. 5(a)).
Regarding claim 3, Liu teaches that the combiner circuit (Fig. 5(a)) includes a first coil electrically coupled between the reference terminal and the quadrature phase terminal (coil between P1 and P2) and a second coil electrically coupled between the in phase terminal and the isolation terminal (coil between P3 and P4), the first coil being magnetically coupled to the second coil (the coils are part of a 1:1 transformer per section E paragraph 2, therefore they are magnetically coupled).
Regarding claim 4, Liu teaches in Fig. 5(a), a first capacitor coupled between the in phase terminal and a DC terminal (capacitor between P3 and ground); a second capacitor coupled between the quadrature phase terminal and the DC terminal (capacitor between P2 and ground); a third capacitor coupled between the reference terminal and the DC terminal (capacitor between P1 and ground); a fourth capacitor coupled between the isolation terminal and the DC terminal (capacitor between P4 and ground); a fifth capacitor coupled between the quadrature phase terminal and the isolation terminal (capacitor between P2 and P4); and a sixth capacitor coupled between the in-phase terminal and the reference terminal (capacitor between P1 and P3).
Regarding claim 5, Liu teaches in Figure 5. (b), that the first, second, third, fourth, fifth, and sixth capacitors are on-chip capacitors (via Metal stack up and compact layout for the transformer-based quadrature hybrid).
Regarding claim 6, Liu teaches that the first, second, third, fourth, fifth, and sixth capacitors could be off-chip capacitors in first paragraph of section E. Liu discloses that “A lumped-element design using a coupled-inductor pair and a capacitor network obtains comparable behavior as branch line coupler and small footprint [44]–[46]”.
Regarding claim 7, Liu teaches (in Fig. 5(a)), further labeled in Figure I of the present office action below, that the first coil has a first center tap terminal (Center tap 1), the second coil has a second center tap terminal (Center tap 2), and the apparatus further comprises: a first capacitor coupled between the in-phase terminal and a DC terminal (capacitor between P3 and ground); a second capacitor coupled between the quadrature phase terminal and the DC terminal (capacitor between P2 and ground); a third capacitor coupled between the reference terminal and the DC terminal (capacitor between P1 and ground); a fourth capacitor coupled between the isolation terminal and the DC terminal (capacitor between P4 and ground); a fifth capacitor coupled between the first center tap terminal and the DC terminal (capacitor between Center tap 1 ground); a seventh capacitor coupled between the quadrature phase terminal and the isolation terminal (capacitor between P2 and P4); an eighth capacitor coupled between the in-phase terminal and the reference terminal (capacitor between P3 and P1); and a ninth capacitor coupled between the first and second center tap terminals (capacitor between Center tap 1 and Center tap 2).
PNG
media_image1.png
366
402
media_image1.png
Greyscale
Figure I: Fig. 5(a) of Liu labeled by Examiner
Regarding claim 8, Liu teaches in Figure 5. (b), that the first, second, third, fourth, fifth, and sixth capacitors are on-chip capacitors (via Metal stack up and compact layout for the transformer-based quadrature hybrid).
Regarding claim 9, Liu teaches that the first, second, third, fourth, fifth, and sixth capacitors could be off-chip capacitors in first paragraph of section E. Liu discloses that “A lumped-element design using a coupled-inductor pair and a capacitor network obtains comparable behavior as branch line coupler and small footprint [44]–[46]”.
Regarding claim 10, Liu teaches that the first and second coils are part of a transformer (the coils are part of a 1:1 transformer per section E paragraph 2).
Regarding claim 11, Liu teaches that wherein an inductance (L) of each of the first (coil with center tap 1) and second coils (coil with center tap 2) is based on a target back-off level at the combiner output (ideal back-off bandwidth upper limit, Section E, line 2), a load impedance at the combiner output (a frequency independent is the desired load impedance per section C), and an operation frequency (center frequency ω0) of the apparatus (see equation 17).
Regarding claim 12, Liu teaches that the combiner circuit includes at least one of: a branch line hybrid coupler or a lange hybrid coupler (Fig. 5(a) shows a branch line hybrid coupler design).
Regarding claim 13, Liu teaches a coupling factor (K) of the quadrature hybrid combiner is based on a target power back-off level at the combiner output. Per Section E, Liu aims to “push the Doherty back-off bandwidth to the ideal bandwidth upper limit” and accordingly derives a coupling factor formula (see equation 21).
Regarding claim 14, Asbeck teaches that the second amplifier is configured to have a higher output power level than the first amplifier (the second amplifier has a higher supply voltage per claim 9, therefore always has higher output power level).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Liu (A 44–64-GHz mm Wave Broadband Linear Doherty PA in Silicon With Quadrature Hybrid Combiner and Non-Foster Impedance Tuner), in view of Asbeck (WO 2021021934 A1), and further in view of Sharma (US 20210218375 A1).
Regarding claim 16, Sharma teaches that the combiner circuit, the first amplifier, and the second amplifier are part of an integrated circuit (IC) (Summary [006]).
Claims 26 is rejected under 35 U.S.C. 103 as being obvious over Asbeck (WO 2021021934 A1), in view of Liu (A 44–64-GHz mm Wave Broadband Linear Doherty PA in Silicon With Quadrature Hybrid Combiner and Non-Foster Impedance Tuner).
Regarding claim 26, Asbeck teaches receiving a first signal (RFin); responsive to a power level ([0078], line 1) of the first signal being below a threshold (low power levels as mentioned in claim 1); providing a second signal (output of 16, Fig. 1) having a first power level using a first amplifier (16, Fig. 1). Asbeck teaches that responsive to a power level of the first signal being above the threshold (maximum power level): providing a third signal (different output of 16, Fig. 1) having a second power level using the first amplifier (16, Fig. 1) and providing a fourth signal (output of 18, Fig. 1) having a third power level higher than the first and second power levels using a second amplifier (both amplifiers operate at full power per claim 1 and the auxiliary amplifier has higher supply voltage than the main amplifier per claim 9, causing the auxiliary amplifier to have a higher output power level).
Asbeck does not teach that the first amplifier provides power to an in phase terminal of a quadrature hybrid combiner and the second amplifier provides power to a quadrature phase terminal of the quadrature hybrid combiner. Asbeck does not teach providing a fifth signal at a reference terminal of quadrature hybrid combiner based on the second signal or a combination of the third and fourth signals as an output signal.
Liu teaches, in Fig. 1 (b), that the first amplifier (Class AB CR PA) provides power to an in phase terminal (P3) of a quadrature hybrid combiner (Fig. 1. (b))) and the second amplifier (Class C PK PA) provides power to a quadrature phase terminal (P2) of the quadrature hybrid combiner. Liu teaches, in section B.1 and B.2, a fifth signal (output) at a reference terminal (P1) of quadrature hybrid combiner based on the second signal (output Class AB CR PA, note that Class C PK PA will be turned off per section B.2) or a combination of the third and fourth signals as an output signal (output Class AB CR PA and Class C PK PA).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the power amplifier circuit of Asbeck to incorporate a transformer-based quadrature hybrid combiner to enhance the bandwidth for broadband Doherty output matching and maximize isolation between the corresponding ports (reference terminal and isolation terminal, and quadrature phase terminal and in phase terminal) (Liu, Section E, line 3).
Allowable Subject Matter
Claims 15, 17-19 and 20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Regarding claim 15, the prior art references (Liu) teach a first combiner circuit (Fig. 1. (b)), the quadrature phase terminal (P2) is a first quadrature phase terminal, the in-phase terminal (P3) is a first in phase terminal, the reference terminal (P1) is a first reference terminal, and the isolation terminal (P4) is a first isolation terminal. The prior art references does not teach that the apparatus further comprises a second combiner circuit having a second quadrature phase terminal, a second in phase terminal, a second reference terminal, and a second isolation terminal, the second reference terminal coupled to the combiner output, and the second isolation terminal coupled to the DC voltage source; a first switch network coupled between the first amplifier output and the first and second in phase terminals; and a second switch network coupled between the second amplifier output and the first and second quadrature phase terminals.
Regarding claim 17, the prior art references do not teach a transformer having a first coil and a second coil, wherein a first terminal of the first coil is coupled to the DC voltage source, wherein the quadrature phase terminal is coupled to the second amplifier output via the transformer, wherein a second terminal of the first coil is coupled to the second amplifier output, wherein a first terminal of the second coil is coupled to ground, and wherein the second terminal of the second coil is coupled to the quadrature phase terminal.
Regarding claim 19, the prior art references do not teach that the first coil and the second coil (of the transformer in claim 17) have a different number of turns.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AHMED RAYEED whose telephone number is (571)270-7528. The examiner can normally be reached 7:30 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AHMED RAYEED/Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
Prosecution Insights