Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of 1, 3-5,7-9 and 11-20 in the reply filed on 02/27/26 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim (s) 1,3-4, 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yosui( WO 2017/199824) in view of Sakai (WO 2011/058938 A1).
Regarding claim 1, Yosui discloses a multilayer board (Fig.1) comprising: a multilayer body including a first insulator layer (21; Fig.1), a second insulator layer (222), and a third insulator layer (23) laminated in this order in an up-down direction, a first region (see region of 122) in which the first insulator layer, the second insulator layer, and the third insulator layer are located when viewed in the up-down direction and a second region (see region 110) in which the first insulator layer and the third insulator layer are located and the second insulator layer is not located when viewed in the up-down direction (see region 110 where there is no second insulating layer 222), each of the first insulator layer and the third insulator layer including a first main surface (see top surface of 21 and 23) located in the up-down direction and a second main surface located in the up-down direction and a conductor in or on the first insulator layer (see 40 on top surface of 21); and a first conductor layer located on the second main surface of the third insulator layer (see 23 on bottom surface of 23).
Yosui is silent with respect to a plurality of interlayer connection conductors in the multilayer body; wherein the plurality of interlayer connection conductors include one or more first interlayer connection conductors located in the first region and passing through any of the first insulator layer, the second insulator layer, and the third insulator layer in the up-down direction and a second interlayer connection conductor located in the second region and passing through the third insulator layer in the up-down direction; the second interlayer connection conductor is joined to the conductor and the first conductor layer; and an area of the second interlayer connection conductor viewed in the up-down direction is larger than a minimum value of areas of the one or more first interlayer connection conductors viewed in the up-down direction.
Sakai discloses, in Fig. 18 a plurality of interlayer connection conductors in the multilayer body; wherein the plurality of interlayer connection conductors include one or more first interlayer connection conductors located in the first region and passing through any of the first insulator layer (L2) , the second insulator layer (L3), and the third insulator layer (L1) in the up-down direction (see through hole vias in left region 81 of Fig.18) and a second interlayer connection conductor located in the second region (see through hole vias in right 81 region) and passing through the third insulator layer (L1) in the up-down direction; the second interlayer connection conductor is joined to the conductor and the first conductor layer ( conductor on bottom of L1 joins conductor on top of L2;Fig.18) ; and an area of the second interlayer connection conductor viewed in the up-down direction is larger than a minimum value of areas of the one or more first interlayer connection conductors viewed in the up-down direction ( biggest area of through hole via in L1 is larger than smallest area of through hole via in L2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Saka to modify the printed circuit board of Yosui to make electrical connections to perform circuit operations.
Regarding claim 3, a modified Yosui discloses wherein the area of the second interlayer connection conductor viewed in the up-down direction is larger than a maximum value of the areas of the one or more first interlayer connection conductors viewed in the up-down direction( see biggest area of through hole via in L1 is larger than smallest area of through hole via in L2 in Saka).
Regarding claim 4, Yosui fails to specifically discloses, wherein the conductor is a second conductor layer located on the second main surface of the first insulator layer .
Saka discloses a second conductor layer located on the second main surface of the first insulator layer (see conductor on bottom surface of 15c;Fig.8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Saka to modify the printed circuit board of Yosui to make electrical connections to perform circuit operations
Regarding claim 16, a modified Yosui discloses wherein a material of the one or more first interlayer connection conductors is of a same kind as a material of the second interlayer connection conductor (through hole vias of Sakai are made of the same conductive material).
Regarding claim 17, a modified Yosui discloses wherein a material of the first insulator layer, a material of the second insulator layer, and a material of the third insulator layer are a same thermoplastic resin (21 222 and 23 are thermoplastic resin).
Claim (s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yosui( WO 2017/199824) in view of Sakai (WO 2011/058938 A1), as applied to claim 17 above and further in view of Muramatsu et al. (WO 2011/030899 A1).
Regarding claim 18, a modified Yosui fails to specifically disclose wherein the thermoplastic resin includes a liquid crystal polymer or polytetrafluoroethylene.
Muramatsu discloses polytetrafluoroethylene ( see “the base film is not particularly limited. For example, polyimide (PI), polyethylene terephthalate (PET), polyether nitrile (PEN), polytetrafluoroethylene (PTFE), liquid crystal polymer (LCP), epoxy, aramid, etc. Can do. The base film preferably has a thickness of 0.050 mm or less, more preferably 0.030 mm or less, and even more preferably 0.020 mm or less. This is because the thickness of the flexible printed circuit board can be reduced if it is 0.050 mm or less”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Maramatsu to modify the printed circuit board of Yosui to provide good dielectric insulation.
Regarding claim 19, a modified Yosui discloses wherein the multilayer board is made of a flexible material (21 222 and 23 are thermoplastic resin).
Regarding claim 20 it is noted that the limitations of the method steps recited in claim 20 “wherein the first, second, and third insulator layers are fusion-bonded.” are process limitations in a product claim and is treated in accordance with MPEP 2113. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process". In re Thorpe, 777Fo 2d 695,698 USPQ 964, 966 (Fed. Cir.1985). See also MPEP 2113.
Allowable Subject Matter
Claims 5,7-9, 11-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
Regarding claim 5, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the second conductor layer includes a third main surface located in the up-down direction and a fourth main surface located in the up-down direction; and a surface roughness of the third main surface of the second conductor layer is larger than a surface roughness of the fourth main surface of the second conductor layer " in combination with the remaining limitations of the claim 1 and 4
Regarding claim 7-8, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the first conductor layer has a linear shape when viewed in the up-down direction; and a line width of the first conductor layer viewed in the up-down direction in the first region is larger than a line width of the first conductor layer viewed in the up-down direction in the second region." in combination with the remaining limitations of the claim 1.
Regarding claim 9, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the conductor is a fourth interlayer connection conductor located in the second region and passing through the first insulator layer in the up-down direction" in combination with the remaining limitations of the claim 1.
Regarding claim 11, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the first conductor layer includes a third main surface located in the up-down direction and a fourth main surface located in the up-down direction; and a surface roughness of the third main surface of the first conductor layer is larger than a surface roughness of the fourth main surface of the first conductor layer" in combination with the remaining limitations of the claim 1.
Regarding claim 12, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the multilayer body includes a fourth insulator layer; wherein the fourth insulator layer, the first insulator layer, the second insulator layer, and the third insulator layer laminated in this order in the up-down direction; and the fourth insulator layer is located in the first region and is not in contact with a boundary between the first region and the second region" in combination with the remaining limitations of the claim 1.
Regarding claim 13, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the multilayer body includes a fifth insulator layer, a fourth insulator layer, the first insulator layer, the second insulator layer, and the third insulator layer laminated in this order in the up-down direction; the fifth insulator layer is located in the first region and the second region; and the fourth insulator layer is located in the first region and is not in contact with a boundary between the first region and the second region" in combination with the remaining limitations of the claim 1.
Regarding claim 14-15, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein a thickness of the second insulator layer in the up-down direction decreases toward a boundary between the first region and the second region." in combination with the remaining limitations of the claim 1.
Therefore, prior art of record neither anticipates nor renders obvious the instantapplication claimed invention as a whole either taken alone or in combination.
Any comments considered necessary by applicant must be submitted no laterthan the payment of the issue fee and, to avoid processing delays, should preferablyaccompany the issue fee. Such submissions should be clearly labeled "Comments onStatement of Reasons for Allowance."
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2848
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