DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/1/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
Fig. 9 is objected to because it is unclear which cross section of fig. 8 is being depicted. The brief description of the drawings describes fig. 9 and a cross section of fig. 8, however there is no cut line on figure 8 to tell where the cross section is being cut out from. Furthermore, the axes on both of the drawings are the same even though they are two different views.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 12, 13, 15, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakata (US 2021/0398950).
As to claim 1, Nakata teaches a semiconductor module (7, figs. 2 and 4) comprising:
a housing (71, 72, and 81) that has a housing space ([0051]);
a semiconductor device (1) that is arranged in the housing space ([0021]), and that has a chip (3, [0021] and [0045]) having:
a main surface (top surface),
a main surface electrode (32f) arranged on the main surface ([0023]),
a terminal electrode (38) arranged on the main surface electrode (32f, [0032]), and
a sealing insulator (6) covering a periphery of the terminal electrode (38) on the main surface such as to expose a part of the terminal electrode (fig. 2, top surface of terminal 38 is exposed, [0034]); and
an insulating gel-like filling (80) agent that is filled in the housing space (fig. 4) such as to contact the sealing insulator (6), and that seals the semiconductor device (1) in the housing space (fig. 4, [0055]).
As to claim 2, Nakata further teaches the gel-like filling agent (80) is filled up to a height position at which an entirety of the semiconductor device is covered in the housing space (fig. 4).
As to claim 3, Nakata further teaches the sealing insulator (6) is thicker than the main surface electrode (fig. 4, sealing insulator 6 is thicker than the entire SC device 1, therefore it is also thicker than the electrode within the device).
As to claim 4, Nakata further teaches the sealing insulator (6) is thicker than the chip (fig. 4, see above reasoning).
As to claim 5, Nakata further teaches the sealing insulator (6) includes a thermosetting resin, and the gel-like filling agent includes a silicone gel ([0034] and [0055]).
As to claim 6, Nakata further teaches the gel-like filling agent (80) contacts the terminal electrode (38) and the sealing insulator (6) and does not contact the main surface electrode (32f, figs. 2 and 4, 80 contacts the top of 38 and the top and sides of 6. 32f is surrounded by 6, thus 80 would not contact 32f).
As to claim 7, Nakata further teaches the terminal electrode (38) is arranged on the main surface electrode (32f) at an interval from a peripheral edge of the main surface electrode (32f), and the sealing insulator covers a peripheral edge portion of the main surface electrode and the terminal electrode (fig. 2, 6 covers sidewalls of 38 and insulating layer 36, which is on the peripheral edge of 32f).
As to claim 8, Nakata further teaches the terminal electrode (38) has a terminal surface (top) and a terminal side wall (sides of 38), the sealing insulator (6) covers the terminal side wall such as to expose the terminal surface (fig. 2), and the gel-like filling agent (80) has a part that directly covers the terminal surface (fig. 4, the sidewalls are covered by 6 and the top surface is covered by 80).
As to claim 9, Nakata further teaches the sealing insulator (6) has an insulating main surface that forms a single flat surface with the terminal surface (fig, 2, 6 is flush with the top surface of 38), and the gel-like filling agent (80) has a part that directly covers the insulating main surface (fig. 4).
As to claim 12, Nakata further teaches an insulating film (36) that partly covers the main surface electrode (32f), and the sealing insulator (6) has a part that covers the insulating film (36, fig. 2, [0042]).
As to claim 13, Nakata further teaches the gel-like filling agent does not contact the insulating film (figs. 2 and 4, the insulating film 36 is covered by 8, thus 80 would not contact the insulating film 36).
As to claim 15, Nakata further teaches the insulating film (36) includes any one of or both of an inorganic insulating film and an organic insulating film ([0042]).
As to claim 20, Nakata further teaches a wiring (4) arranged in the housing space (fig. 2, [0029]); and a conducting wire (5) connected to the wiring (4) and the semiconductor device (3, [0042]); wherein the gel-like filling agent (80) seals the wiring, the semiconductor device, and the conducting wire (fig. 4, 80 seals everything pertaining to the semiconductor device 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16-29 are rejected under 35 U.S.C. 103 as being unpatentable over Nakata.
As to claims 16-19, Nakata teaches chip 3 is a MOSFET ([0023] and [0045]). MOSFETs are known to have epitaxial layers on their surface (i.e. sources and drains), to which contacts such as 38 connect.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed that the main surface would contain the epitaxial layer for the reasons stated above.
Furthermore, determining the thickness of the epitaxial layer and the semiconductor materials and structure of the chip and its substrate would have been obvious so as to fabricate a device using industrially tested and accepted parameters and materials. It is noted that the Applicant has not shown that these limitations are novel and would not have been found through routine experimentation.
Allowable Subject Matter
Claims 10, 11, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art fails to teach a combination of all of the features in the claims. As to claim 10, Nakata fails to teach the chip has a side surface, and the gel-like filling agent has a part that directly covers the side surface. The sealing insulator 6 very much covers the entire chip 3 (fig. 2), thus the gel-like filling agent would not have a part that directly covers the side surface of the chip 3.
As to claim 14, Nakata fails to teach the terminal electrode has a part that directly covers the insulating film. Fig. 2 clearly shows the insulating film 36 on the sidewall of the terminal electrode 38, thus the terminal electrode 38 does not have a part that directly covers the insulating film.
Claim 11 is allowable at least because it depends from allowable claim 10.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any response to this Office Action should be faxed to (571) 273-8300 or mailed to:
Commissioner for Patents
P.O. Box 1450
Alexandria, VA 22313-1450
Hand-Delivered responses should be brought to:
Customer Service Window
Randolph Building
401 Dulany Street
Alexandria, VA 22313
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
7/20/26
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