DETAILED ACTION
This Office Action is in response to the application filed on 01 May 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claims 13 and 18, claims 13 and 18 recite in pertinent part “wherein the second electrode of the first pixel and the second electrode of the second pixel” however the only antecedent basis for “the second electrode” is of “wherein the capacitor includes a first electrode and a second electrode.” For the purposes of examination, the phrase “the second electrode” will be interpreted as second electrodes of the recited capacitors.
Claims 14-17, 19, and 20 are directly or indirectly dependent from claims 13 and 18 and therefore inherit the indefinite limitations discussed above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10-13, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipation by Takeda et al. (US 2022/0285410 A1; hereinafter Takeda).
In regards to claim 1, Takeda teaches, e.g. in figs. 1 and 13, an image sensor comprising:
a plurality of pixels (PR/PG/PB) [0058], each of which includes a photovoltaic device (PD1/PD2) configured to convert incident light into charge [0052], and a capacitor configured to store the charge [0045],
wherein the capacitor of each of the plurality of pixels comprises:
a first electrode and a second electrode that overlap each other ([0045]: e.g. MIS capacitor has electrodes that overlap in a direction); and
a dielectric layer that is between the first electrode and the second electrode ([0045]: e.g. MIS capacitor),
wherein the plurality of pixels include a first pixel (e.g. (PR)) and a second pixel (e.g. (PG)) adjacent to each other (fig. 1C), and
wherein the second electrode of the first pixel and the second electrode of the second pixel are integral with each other (fig. 1C: instances of (250) span between two pixels, e.g. instance of (250) between (PR) and (PG) in (PMD) under (DT)).
In regards to claim 10, Takeda teaches the limitations discussed above in addressing claim 1. Takeda further teaches, e.g. in figs. 1 and 13, the limitations wherein the plurality of pixels further include a third pixel and a fourth pixel adjacent to the first pixel and the second pixel, and wherein the second electrode of the first pixel, the second electrode of the second pixel, the second electrode of the third pixel, and the second electrode of the fourth pixel are integral with each other (fig. 13: e.g. (PX1-PX4)).
In regards to claim 11, Takeda teaches the limitations discussed above in addressing claim 10. Takeda further teaches, e.g. in figs. 1 and 13, the limitations wherein the first pixel, the second pixel, the third pixel, and the fourth pixel are arranged along a row direction and a column direction (fig. 13: e.g. (PX1-PX4)).
In regards to claim 12, Takeda teaches the limitations discussed above in addressing claim 1. Takeda further teaches, e.g. in figs. 1 and 13, the limitations wherein the second electrodes of the plurality of pixels are integral with each other (fig. 1C: instances of (250) span between two pixels, e.g. instance of (250) between (PR) and (PG) in (PMD) under (DT)).
In regards to claim 13, Takeda teaches, e.g. in figs. 1 and 13, an image sensor comprising:
a plurality of pixels (PR/PG/PB) [0058], each of which comprises:
a photovoltaic device (PD1/PD2) configured to convert incident light into charge [0052];
a first floating diffusion zone (fig. 13; [0106]) and a second floating diffusion zone (fig. 13; [0106]) that are coupled to the photovoltaic device [0052];
a transfer transistor (e.g. (25)) that is coupled between the photovoltaic device and the first floating diffusion zone [0045]; and
a dual conversion gain transistor ([0052]: amplifying transistor for electric charges from (PD1) and electric charges from (PD2)) that is coupled between the first floating diffusion zone and the second floating diffusion zone [0052],
wherein the second floating diffusion zone includes a capacitor [0045],
wherein the capacitor includes a first electrode and a second electrode that overlap each other ([0045]: e.g. MIS capacitor has electrodes that overlap in a direction), and a dielectric layer that is between the first electrode and the second electrode ([0045]: e.g. MIS capacitor),
wherein the plurality of pixels include a first pixel (e.g. (PR)) and a second pixel (e.g. (PG)) adjacent to each other (fig. 1C), and
wherein the second electrode of the first pixel and the second electrode of the second pixel are integral with each other (fig. 1C: instances of (250) span between two pixels, e.g. instance of (250) between (PR) and (PG) in (PMD) under (DT)).
In regards to claim 18, Takeda teaches, e.g. in figs. 1 and 13, an image sensor comprising:
a plurality of pixels (PR/PG/PB) [0058], each of which comprises:
a light transmission layer (CFR/CFG/CFB) [0058];
a photoelectric conversion layer (PD1/PD2) configured to convert light passing through the light transmission layer into an electrical signal [0052];
a transfer transistor (e.g. (25)) that is coupled to the photoelectric conversion layer [0045];
a first floating diffusion zone (fig. 13; [0106]) and a dual conversion gain transistor ([0052]: amplifying transistor for electric charges from (PD1) and electric charges from (PD2)) that are coupled to the transfer transistor [0052]; and
a capacitor that is coupled to the dual conversion gain transistor [0045],
wherein the capacitor includes a first electrode and a second electrode that overlap each other ([0045]: e.g. MIS capacitor has electrodes that overlap in a direction), and a dielectric layer that is between the first electrode and the second electrode ([0045]: e.g. MIS capacitor),
wherein the plurality of pixels include a first pixel (e.g. (PR)) and a second pixel (e.g. (PG)) adjacent to each other (fig. 1C), and
wherein the second electrode of the first pixel and the second electrode of the second pixel are integral with each other (fig. 1C: instances of (250) span between two pixels, e.g. instance of (250) between (PR) and (PG) in (PMD) under (DT)).
In regards to claim 19, Takeda teaches the limitations discussed above in addressing claim 18. Takeda further teaches, e.g. in figs. 1 and 13, the limitations wherein the plurality of pixels further include a third pixel and a fourth pixel adjacent to the first pixel and the second pixel, and wherein the second electrode of the first pixel, the second electrode of the second pixel, the second electrode of the third pixel, and the second electrode of the fourth pixel are integral with each other (fig. 13: PX1-PX4).
In regards to claim 20, Takeda teaches the limitations discussed above in addressing claim 18. Takeda further teaches, e.g. in figs. 1, and 13, the limitations wherein the second electrodes of the plurality of pixels are integral with each other (fig. 1C: instances of (250) span between two pixels, e.g. instance of (250) between (PR) and (PG) in (PMD) under (DT)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, 5, 6, 14, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeda.
In regards to claim 2, Takeda teaches the limitations discussed above in addressing claim 1. Takeda teaches in a separate embodiment, the limitations wherein the first electrode of the capacitor is coupled to the photovoltaic device, and wherein the second electrode of the capacitor is coupled to a ground (fig. 2: e.g. (CINC2) is connected to a ground with another side indirectly connected to (PD2)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to combine the limitations taught by the different embodiments as taught by Takeda to tune a capacitance of a device element for desired applications (Takeda [0096]).
In regards to claim 3, Takeda teaches the limitations discussed above in addressing claim 1. Takeda teaches in a separate embodiment, the limitations further comprising:
a first wiring line that is coupled between the photovoltaic device and the first electrode of the capacitor (fig. 2: wiring (e.g. M1/M2/M3) between (CEL2) and (PD2));
a first insulating layer (fig. 1C: e.g. (PMD)) that is between the first electrode of the capacitor and the first wiring line (fig. 2); and
a first via that extends through the first insulating layer so as to couple the first electrode of the capacitor and the first wiring line together [0056].
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to combine the limitations taught by the different embodiments as taught by Takeda to tune a capacitance of a device element for desired applications (Takeda [0096]).
In regards to claim 5, Takeda teaches the limitations discussed above in addressing claim 3. Takeda teaches in a separate embodiment, the limitations wherein the first electrode of the first pixel and the first electrode of the second pixel are spaced apart from each other (e.g. fig. 1C: some electrodes like (251/254) are separated from one another). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to combine the limitations taught by the different embodiments as taught by Takeda to tune a capacitance of a device element for desired applications (Takeda [0096]).
In regards to claim 6, Takeda teaches the limitations discussed above in addressing claim 5. Takeda teaches in a separate embodiment, the limitations further comprising a second via that extends through the first insulating layer and the dielectric layer so as to be coupled to the first wiring line (fig. 1C: e.g. metallization layers in (ILD)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to combine the limitations taught by the different embodiments as taught by Takeda to tune a capacitance of a device element for desired applications (Takeda [0096]).
In regards to claim 14, Takeda teaches the limitations discussed above in addressing claim 13. Takeda teaches in a separate embodiment, the limitations further comprising:
a first wiring line that is coupled between the photovoltaic device and the first electrode of the capacitor (fig. 2: wiring (e.g. M1/M2/M3) between (CEL2) and (PD2));
a first insulating layer (fig. 1C: e.g. (PMD)) that is between the first electrode of the capacitor and the first wiring line (fig. 2); and
a first via that extends through the first insulating layer so as to couple the first electrode of the capacitor and the first wiring line together [0056].
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to combine the limitations taught by the different embodiments as taught by Takeda to tune a capacitance of a device element for desired applications (Takeda [0096]).
In regards to claim 16, Takeda teaches the limitations discussed above in addressing claim 14. Takeda teaches in a separate embodiment, the limitations wherein the first electrode of the first pixel and the first electrode of the second pixel are spaced apart from each other (e.g. fig. 1C: some electrodes like (251/254) are separated from one another). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to combine the limitations taught by the different embodiments as taught by Takeda to tune a capacitance of a device element for desired applications (Takeda [0096]).
Allowable Subject Matter
Claims 4, 7-9, 15, and 17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
In regards to claims 4, 7-9, 15, and 17, Takeda teaches the limitations as discussed above in addressing claims 3, 6, 14, and 16. Takeda appears to be silent as to the limitations wherein the second electrode has first and second holes that have the layout as set forth in claims 4, 7-9, 15, and 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William (Blake) Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Primary Patent Examiner, Art Unit 2812
Prosecution Insights