DETAILED ACTION
This action is responsive to the election received on 09/21/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (Figure 2) in the reply filed on 09/21/2026 is acknowledged. Claim(s) 6 and 8-20 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an applications filed in REPUBLIC OF KOREA on 06/08/2023 and 11/01/2023.
Applicant cannot rely upon the certified copy of the foreign priority applications to overcome this rejection because a translation of said applications have not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/01/2024 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, and 7 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2023/0197604 A1; Kim et al.; 06/2023; (“Kim”).
Regarding Claim 1. Kim discloses A semiconductor device (Figures 13 and 15 where Figure 15 is a zoomed in section of Figure 13 according to [0021], semiconductor device according to [0020]) comprising:
a via pattern (#110, Figure 13, lower wiring structure) in a first interlayer insulating film (#150, Figure 13, interlayer insulating film #110 is inside of); and
a wiring pattern (#210, Figure 13, upper wiring structure) that extends in a first direction and is on the first interlayer insulating film and the via pattern (Figure 13, #210 extends in a first direction #D2 and is on #110 and #150),
wherein the wiring pattern (#210) comprises a lower wiring line (#211, Figure 13, upper barrier film made of conductive metal according to [0087]) and an upper wiring line on the lower wiring line (#212, Figure 13, second upper barrier film made of conductive metal according to [0088] and on #211),
wherein the lower wiring line and the upper wiring line are stacked in a second direction (Figure 13, #211 and #212 are stacked in a second direction #D3),
wherein the lower wiring line is between the via pattern and the upper wiring line and is on an upper surface of the via pattern (Figure 13, #211 is between #110 and #212 and is directly on an upper surface of #110),
wherein a first portion of the lower wiring line is on the upper surface of the via pattern and has a first thickness (Figure 15, a first portion of #211 between the #112s is directly on an upper surface of #110 and has a first thickness in the vertical direction), and
wherein a second portion of the lower wiring line is on an upper surface of the first interlayer insulating film and has a second thickness (Figure 15, a second portion of #211 outside the #112s is directly on an upper surface of #150 and has a second thickness in the vertical direction) that is different from the first thickness (Figure 15, the thickness of the portion of #211 between and immediately adjacent to the #112s is greater than the thickness of the portion outside the #112s).
Regarding Claim 2. Kim discloses The semiconductor device of claim 1, wherein the first thickness is greater than the second thickness (Figure 15, the thickness of the portion of #211 between and immediately adjacent to the #112s is greater than the thickness of the portion outside the #112s).
Regarding Claim 3. Kim discloses The semiconductor device of claim 1, wherein:
the upper wiring line comprises a first metal comprising molybdenum (Mo), ruthenium (Ru), or tungsten (W) ([0088], #212 may comprise tungsten in the form of WN),
the lower wiring line comprises a second metal comprising ruthenium (Ru), cobalt (Co), or tungsten (W) ([0087], #211 may comprise ruthenium (Ru)), and
the first metal and the second metal are different ([0087]-[0088], the first metal WN and the second metal Ru are different).
Regarding Claim 5. Kim discloses The semiconductor device of claim 1, wherein in the second direction, the upper surface of the via pattern is lower than the upper surface of the first interlayer insulating film (Figures 13 and 15, in the second direction #D3 the upper surface of #113 of #110 is lower than the upper surface of #150, particularly at the left and right edges of #113).
Regarding Claim 7. Kim discloses The semiconductor device of claim 1, wherein:
the first interlayer insulating film comprises a first lower interlayer insulating film and a first upper interlayer insulating film on the first lower interlayer insulating film (Figure 13, the first interlayer insulating film may be interpreted as comprising #150, a first interlayer insulating film, as a first lower interlayer insulating film, and #155, a first etch stopper film, as a first upper interlayer insulating film on #150 and made of insulating material according to [0071]),
the lower wiring line contacts the first upper interlayer insulating film (Figures 13 and 15, #211 directly contacts #155),
the first upper interlayer insulating film comprises silicon oxide ([0071], #155 comprises silicon oxide in the form of SiON or SiOCN, both of which comprise silicon oxide, as examples), and
the first lower interlayer insulating film comprises a material having a dielectric constant that is less than a dielectric constant of silicon oxide ([0037]-[0038], #150 comprises various low-k materials having a lower dielectric constant than silicon oxide such as SiCOH).
Claim(s) 1-3, 5, and 7 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2022/0310506 A1; Park et al.; 09/2022; (“Park”).
Regarding Claim 1. Park discloses A semiconductor device (Figure 7, semiconductor device according to [0017]) comprising:
a via pattern (#310, Figure 7, conductive insertion pattern) in a first interlayer insulating film (#160, Figure 7, second interlayer insulating layer #310 is located in); and
a wiring pattern (#210, Figure 7, first upper wiring structure) that extends in a first direction and is on the first interlayer insulating film and the via pattern (Figure 7, #210 extends in a first #D2 direction and is directly on #160 and #310),
wherein the wiring pattern (#210) comprises a lower wiring line (#210a, Figure 7, upper barrier conductive layer) and an upper wiring line on the lower wiring line (#210b, Figure 7, upper filling conductive layer on #210a),
wherein the lower wiring line and the upper wiring line are stacked in a second direction (Figure 7, #210a and #210b are stacked in a second #D3 direction),
wherein the lower wiring line is between the via pattern and the upper wiring line (Figure 7, #210a is between #310 and #210b) and is on an upper surface of the via pattern (Figure 7, #210a is directly on an upper surface of #310),
wherein a first portion of the lower wiring line is on the upper surface of the via pattern and has a first thickness (Figure 7, a first portion of #210a is on the upper surface of #310 and has a first thickness where the first portion is the entire portion which extends between the bottommost surface of #210b and the top surface of #155), and
wherein a second portion of the lower wiring line is on an upper surface of the first interlayer insulating film and has a second thickness (Figure 7, a second portion of #210a is on the upper surface of #160 and has a second thickness where the second portion is the portion which extends between the second bottommost surface of #210b and the top surface of #160) that is different from the first thickness (Figure 7, the two portions of #210a have different thicknesses due to the thicker part of the first portion which is immediately adjacent to #310).
Regarding Claim 2. Park discloses The semiconductor device of claim 1, wherein the first thickness is greater than the second thickness (Figure 7, the two portions of #210a have different thicknesses due to the thicker part of the first portion which is immediately adjacent to #310).
Regarding Claim 3. Park discloses The semiconductor device of claim 1, wherein:
the upper wiring line comprises a first metal comprising molybdenum (Mo), ruthenium (Ru), or tungsten (W) ([0074], #210b may have the same materials as #110b which may include molybdenum according to [0045]),
the lower wiring line comprises a second metal comprising ruthenium (Ru), cobalt (Co), or tungsten (W) ([0074], #210a may have the same materials as #110a which may include cobalt according to [0044]), and
the first metal and the second metal are different ([0074] and [0044]-[0045], the material options for #210a/#110a and #210b/#110b are different from one another).
Regarding Claim 5. Park discloses The semiconductor device of claim 1, wherein in the second direction, the upper surface of the via pattern is lower than the upper surface of the first interlayer insulating film (Figure 7, the upper surface of #310 in the second #D3 direction is lower than the upper surface of #160).
Regarding Claim 7. Park discloses The semiconductor device of claim 1, wherein:
the first interlayer insulating film comprises a first lower interlayer insulating film and a first upper interlayer insulating film on the first lower interlayer insulating film (Figure 7, the first interlayer insulating film may be interpreted as comprising #155, a first etch stop layer, as a first lower interlayer insulating film made of insulating material according to [0052], and #160, second interlayer insulating layer, as a first upper interlayer insulating film on #155),
the lower wiring line contacts the first upper interlayer insulating film (Figure 7, #210a directly contacts #160),
the first upper interlayer insulating film comprises silicon oxide ([0051], #160 may comprise silicon oxide), and
the first lower interlayer insulating film comprises a material having a dielectric constant that is less than a dielectric constant of silicon oxide ([0052], #155 may comprise SiOC which is known to have a lower dielectric constant than silicon oxide).
Claim(s) 1-3 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0148289 A1; Seo et al.; 05/2019; (“Seo”).
Regarding Claim 1. Seo discloses A semiconductor device (Figures 1-4, various views of a semiconductor device according to [0011]-[0014]) comprising:
a via pattern (#310, Figure 4, via) in a first interlayer insulating film (#201 and #202, Figure 2, [0038], first and second regions of first interlayer insulating film which #310 is located in); and
a wiring pattern (#410, Figure 4, first upper wiring) that extends in a first direction and is on the first interlayer insulating film and the via pattern (Figure 4, #410 extends in a first #D2 direction and is on #310 and the combination of #201 and #202),
wherein the wiring pattern (#410) comprises a lower wiring line (#412, Figure 4, upper barrier film made of conductive material according to [0061]) and an upper wiring line on the lower wiring line (#411, Figure 4, upper wiring film),
wherein the lower wiring line and the upper wiring line are stacked in a second direction (Figure 4, #412 and #411 are stacked in a second #D3 direction),
wherein the lower wiring line is between the via pattern and the upper wiring line and is on an upper surface of the via pattern (Figure 4, #412 is between #310 and #411 and is directly on an upper surface of #310),
wherein a first portion of the lower wiring line is on the upper surface of the via pattern and has a first thickness (Figure 4, the portion of #412 which is directly on #310 has a first thickness between the bottom surface of #411 and the top surface of #310 following a curved path), and
wherein a second portion of the lower wiring line is on an upper surface of the first interlayer insulating film and has a second thickness (Figure 4, the portion of #412 which is directly on #201 has a second planar thickness between the bottom surface of #411 and the top surface of #202) that is different from the first thickness (Figure 4, the curved portions of #412 have a greater vertical thickness than the planar portions of #412).
Regarding Claim 2. Seo discloses The semiconductor device of claim 1, wherein the first thickness is greater than the second thickness (Figure 4, the curved portions of #412 have a greater vertical thickness than the planar portions of #412).
Regarding Claim 3. Seo discloses The semiconductor device of claim 1, wherein:
the upper wiring line (#411) comprises a first metal comprising molybdenum (Mo), ruthenium (Ru), or tungsten (W) ([0063], #411 may include just tungsten (W)),
the lower wiring line (#412) comprises a second metal comprising ruthenium (Ru), cobalt (Co), or tungsten (W) ([0061], #412 may include cobalt (Co)), and
the first metal and the second metal are different ([0061] and [0063], #411 may include pure tungsten while #412 does not offer that option such that they are different).
Regarding Claim 5. Seo discloses The semiconductor device of claim 1, wherein in the second direction, the upper surface of the via pattern is lower than the upper surface of the first interlayer insulating film (Figure 4, the upper surface of #310 in the second #D3 direction is lower than the upper surface of the combination of #201 and #202).
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0013146 A1; Wang et al.; 01/2021; (“Wang”).
Regarding Claim 1. Wang discloses A semiconductor device (Figure 19, interconnect structure for a semiconductor device) comprising:
a via pattern (#60, Figure 19, conductive via) in a first interlayer insulating film (#34, Figure 19, single dielectric layer); and
a wiring pattern (#84 and #94, Figure 19, conductive line and conductive feature) that extends in a first direction and is on the first interlayer insulating film and the via pattern (Figure 19, the combination of #84 and #94 extends in the horizontal direction and is on #34 and #60),
wherein the wiring pattern comprises a lower wiring line (#84, Figure 19, conductive line) and an upper wiring line on the lower wiring line (#94, Figure 19, conductive feature on #84),
wherein the lower wiring line and the upper wiring line are stacked in a second direction (Figure 19, #84 and #94 are stacked in a vertical direction),
wherein the lower wiring line is between the via pattern and the upper wiring line and is on an upper surface of the via pattern (Figure 19, #84 is between #94 and #60 and #84 is on an upper surface of #60, see [0050] which describes how #80, which is used to make #84, alloys with #60 at the interface #70),
wherein a first portion of the lower wiring line is on the upper surface of the via pattern and has a first thickness (Figure 19, a central portion of #84 is on #60 and has a first thickness), and
wherein a second portion of the lower wiring line is on an upper surface of the first interlayer insulating film and has a second thickness (Figure 19, an edge portion of #84 is on #34 and has a second thickness) that is different from the first thickness (Figure 19, the thickness of the central portion of #84 near the edges of #60 is greater than the thickness at the edge of #84; see also Figure 18 which shows an alternative configuration for #60 which would cause the central portion of #84 to be much thicker).
Regarding Claim 2. Wang discloses The semiconductor device of claim 1, wherein the first thickness is greater than the second thickness (Figure 19, the thickness of the central portion of #84 near the edges of #60 is greater than the thickness at the edge of #84; see also Figure 18 which shows an alternative configuration for #60 which would cause the central portion of #84 to be much thicker).
Regarding Claim 4. Wang discloses The semiconductor device of claim 1, further comprising:
a second interlayer insulating film (#92, Figure 19, fourth dielectric layer) on the first interlayer insulating film (Figure 19, #92 is on #34) ,
wherein the upper wiring line is in and contacts the second interlayer insulating film (Figure 19, #94 is in and directly contacts #92).
Regarding Claim 5. Wang discloses The semiconductor device of claim 1, wherein in the second direction, the upper surface of the via pattern is lower than the upper surface of the first interlayer insulating film (Figure 19, the upper surface of #60 is lower than the upper surface of #34 in the vertical direction).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2020/0105664 A1; Han et al.; 04/2020 – Figure 10 discloses a multi-layer wiring structure on top of a via in two separate insulating layers wherein the lower layer of the wiring structure is on and in direct contact with both the via and the lower insulating layer.
US 2018/0358262 A1; Lu et al.; 12/2018 – Figure 16 discloses a multi-layer wiring structure on top of a via in two separate insulating layers wherein the lower layer of the wiring structure is on and in direct contact with both the via and the lower insulating layer.
US 2024/0153848 A1; Yoo et al.; 05/2024 – Figure 14 discloses a multi-layer wiring structure on top of a via in two separate insulating layers wherein the lower layer of the wiring structure is on and in direct contact with both the via and the lower insulating layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE KIM can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
