Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on August 10, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6 and 13-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (PG Pub 2022/0130759 A1) and Chang et al (PG Pub 2024/0064953 A1).
Regarding claim 1, Huang teaches a semiconductor integrated circuit (IC) device comprising: a first source/drain region (260, fig. 14) connected to a second source/drain region (260) by a plurality of active channels (215, figs. 2E and 14); a backside contact (282, paragraph [0039]) that is directly coupled to the first source/drain region; and a backside dielectric plug (408, paragraph [0047]) that is directly coupled to the second source/drain region and that is directly coupled to the backside contact.
Huang does not teach a frontside contact that is directly coupled to the second source/drain region.
In the same field of endeavor, Chang teaches a frontside contact (336, fig. 11A) that is directly coupled to the second source/drain region (114N), for the benefit of providing a SRAM cell (figs. 6 and 11A, and abstract).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a frontside contact that is directly coupled to the second source/drain region for the benefit of providing a SRAM cell.
Regarding claim 2, Huang teaches the semiconductor IC device of claim 1, wherein a portion of a sidewall of the backside dielectric plug is directly coupled to a portion of a sidewall of the backside contact (fig. 14).
Regarding claim 3, Chang teaches the semiconductor IC device of claim 2, further comprising: a frontside back end of line network (MLI 510, fig. 11A, paragraph [0049]) that is connected to the frontside contact.
Regarding claim 4, Huang teaches the semiconductor IC device of claim 3, further comprising: a backside back end of line network (284, fig. 14, paragraph [0053]) that is connected to the backside contact and to the backside dielectric plug.
Regarding claim 5, Huang teaches the semiconductor IC device of claim 4, further comprising: a gate (240, fig. 14) that is connected to the plurality of active channels.
Regarding claim 6, Huang teaches the semiconductor IC device of claim 5, wherein the plurality of active channels (215, figs. 2D and 14, paragraph [0020]) are vertically stacked.
Regarding claim 13, Huang in view of Chang teaches (see claim 1) the semiconductor integrated circuit (IC) device comprising: a totality of source/drain regions in the semiconductor IC device, the totality of source/drain regions consisting of first source/drain regions and second source/drain regions; the first source/drain regions are each directly connected to a respective backside contact; and the second source/drain regions are each directly coupled to a respective frontside contact and are each directly coupled to a backside dielectric plug. Furthermore, it would have been obvious to the skilled in the art before the effective filing date of the invention to include more transistors that those shown in fig. 14 of Huang for the known benefit of increasing the storage capacity of the memory storage.
Regarding claim 14, Huang teaches (see claim 2) the semiconductor IC device of claim 13, wherein each backside dielectric plug is directly coupled to one or more of the backside contacts.
Regarding claim 15, Chang teaches (see claim 3) the semiconductor IC device of claim 14, further comprising: a frontside back end of line network that is connected to each of the respective frontside contacts.
Regarding claim 16, Huang teaches (see claim 4) the semiconductor IC device of claim 15, further comprising: a backside back end of line network that is connected to each of the respective backside contacts and that is connected to each of the respective backside dielectric plugs.
Allowable Subject Matter
Claims 7-12 and 17-19 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: prior art does not teach
a backside interlayer dielectric (ILD) directly coupled to the backside contact and directly coupled to the backside dielectric plug (claims 7 and 17).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST.
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/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
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