DETAILED ACTION
This office action is responsive to communication filed on January 27, 2026.
Response to Arguments
Applicant’s arguments with respect to claims 1, 8 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
All previous rejections under 35 USC 112 are hereby removed in view of Applicant’s response.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21 and 22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 21 and 22 each recite “wherein the defective pixel correction process comprises a first correction algorithm for the first type of defective pixel and a second, different correction algorithm for the second type of defective pixel”. However, the Examiner has been unable to find support in the original disclosure for the defective pixel correction process comprising a first correction algorithm for the first type of defective pixel and a second, different correction algorithm for the second type of defective pixel. Therefore, claims 21 and 22 each contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 6-9, 13-15 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sasai (US 6,977,681) in view of Ogino (US 2011/0080505).
Consider claim 1, Sasai teaches:
An apparatus for processing pixel data from a sensor (image processing apparatus, 10, figure 1), the apparatus comprising:
a memory (buffer unit, 4, figure 1) configured to receive the pixel data (“Reference numeral 4 denotes a buffer unit for temporarily storing the replacement information-added image data 3 sequentially output from the replacement unit 2” column 4, lines 3-5); and
one or more processors (interpolation processing unit, 6, figure 1) in communication with the memory (see figure 1, “and 6, an interpolation processing unit for reading out replacement information-added image data 5 stored in the buffer unit 4”, column 4, lines 5-7), the one or more processors (6) configured to:
receive the pixel data (“and 6, an interpolation processing unit for reading out replacement information-added image data 5 stored in the buffer unit 4”, column 4, lines 5-7) comprising a plurality of pixel values (see figure 2C, column 4, lines 49-56), wherein each pixel value of the pixel data is represented by a digital value in a range from 0 to 2n-1 (see D0-Dk and Dd in figure 2C), wherein n is a number of bits of the digital value (see D0-Dk and Dd in figure 2C), wherein one or more digital values in the range from 0 to 2n -1 indicate a defective pixel (The digital value Dd (1D) indicates a defective pixel, column 4, lines 40-56.), and wherein remaining values in the range from 0 to 2n -1 indicate a light intensity value (The remaining values D0-Dk (23) indicate a light intensity value, column 4, lines 49-56, column 4, lines 18-28, column 3, lines 50-54.);
determine whether a particular pixel is defective based on the digital value of the particular pixel; and perform a defective pixel correction process on the particular pixel based on the particular pixel being determined to be defective (“and 6, an interpolation processing unit for reading out replacement information-added image data 5 stored in the buffer unit 4, generating, by interpolation processing, pixel values representing all color information levels for a corresponding interpolation point from the pixel values of a plurality of pixels falling within a predetermined pixel region, and when pixel values used for interpolation processing includes a pixel value whose replacement information represents replacement, performing interpolation processing using an arithmetic expression different from a normal one, and outputting each obtained pixel value as the new image data 9” column 4, lines 5-17).
However, Sasai does not explicitly teach that the one or more digital values include a first digital value indicating a first type of defective pixel and a second digital value indicating a second type of defective pixel, and wherein the defective pixel correction process is based on a type of defective pixel indicated by the digital value for the particular pixel.
Ogino similarly teaches an apparatus (defect detecting correcting section, 208, figure 1) for processing pixel data output from a sensor (image pickup element, 203, paragraphs 0025 and 0026), wherein the pixel data includes a digital value indicating that a pixel is defective (“a defect flag 519 (1 bit) indicating whether or not a defect is formed” paragraph 0075).
However, Ogino additionally teaches that that the pixel data includes a first digital value indicating a first type of defective pixel and a second digital value indicating a second type of defective pixel (Ogino teaches that the pixel data includes “a black/white flag 520 (1 bit) for distinguishing between a white defect (white-spot defective pixel) and a black defect (black-spot defective pixel)” paragraph 0075. A 1-bit flag has first and second digital values (i.e. 0 and 1).), and wherein the defective pixel correction process is based on a type of defective pixel indicated by the digital value for the particular pixel (Defective pixel correction is performed by a defective pixel correcting section (2082, figures 1, 5 and 11), paragraphs 0026, 0033, 0035, 0036 and 0094-0098. The defective pixel correction by the defective pixel correcting section (2082) is performed according to a defect level (K), paragraphs 0094-0096, see figure 11. The defect level (K) is output by a selector (521, figure 5, paragraph 0093) and is based at least in part on the output of a threshold value determining circuit (515), figure 5, paragraph 0091. The output of the threshold value determining circuit (515) is calculated based on the type of defective pixel indicated by the black/white flag (520), see figure 5, paragraphs 0077 and 0080.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the one or more digital values taught by Sasai include a first digital value indicating a first type of defective pixel and a second digital value indicating a second type of defective pixel as taught by Ogino for the benefit of reducing adverse effects resulting from excessively correcting an output signal of a blinking defective pixel (Ogino, paragraph 0107).
Consider claim 2, and as applied to claim 1 above, Sasai does not explicitly teach the type of defective pixel.
Ogino teaches that the one or more digital values include a value 0 and a value 1 in the range from 0 to 2n -1, wherein the value of 0 indicates a first type of defective pixel, and wherein the value 1 indicates a second type of defective pixel (Ogino teaches that the pixel data includes “a black/white flag 520 (1 bit) for distinguishing between a white defect (white-spot defective pixel) and a black defect (black-spot defective pixel)” paragraph 0075. A 1-bit flag has first and second digital values (i.e. 0 and 1).).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the one or more digital values taught by Sasai include a first digital value indicating a first type of defective pixel and a second digital value indicating a second type of defective pixel as taught by Ogino for the benefit of reducing adverse effects resulting from excessively correcting an output signal of a blinking defective pixel (Ogino, paragraph 0107).
Consider claim 6, and as applied to claim 1 above, Sasai further teaches that the defective pixel correction process comprises an interpolation process using digital values of neighboring pixels to the particular pixel (see column 5, lines 44-61 and column 6, lines 24-36).
Consider claim 7, and as applied to claim 1 above, Sasai further teaches that the one or more processors comprise an image signal processor (interpolation processing unit, 6, figure 1, column 4, lines 5-17), and wherein the apparatus further includes a sensor (“an image sensor such as a CCD”, column 3, lines 50-52).
Consider claim 8, Sasai teaches:
A method of processing pixel data from a sensor, the method comprising:
receiving pixel data (“and 6, an interpolation processing unit for reading out replacement information-added image data 5 stored in the buffer unit 4”, column 4, lines 5-7) comprising a plurality of pixel values (see figure 2C, column 4, lines 49-56), wherein each pixel value of the pixel data is represented by a digital value in a range from 0 to 2n -1 (see D0-Dk and Dd in figure 2C), wherein n is a number of bits of the digital value (see D0-Dk and Dd in figure 2C), wherein one or more digital values in the range from 0 to 2n -1 indicate a defective pixel (The digital value Dd (1D) indicates a defective pixel, column 4, lines 40-56.), and wherein remaining values in the range from 0 to 2n -1 indicate a light intensity value (The remaining values D0-Dk (23) indicate a light intensity value, column 4, lines 49-56, column 4, lines 18-28, column 3, lines 50-54.);
determining whether a particular pixel is defective based on the digital value of the particular pixel; and performing a defective pixel correction process on the particular pixel based on the particular pixel being determined to be defective (“and 6, an interpolation processing unit for reading out replacement information-added image data 5 stored in the buffer unit 4, generating, by interpolation processing, pixel values representing all color information levels for a corresponding interpolation point from the pixel values of a plurality of pixels falling within a predetermined pixel region, and when pixel values used for interpolation processing includes a pixel value whose replacement information represents replacement, performing interpolation processing using an arithmetic expression different from a normal one, and outputting each obtained pixel value as the new image data 9” column 4, lines 5-17).
However, Sasai does not explicitly teach that the one or more digital values include a first digital value indicating a first type of defective pixel and a second digital value indicating a second type of defective pixel, and wherein the defective pixel correction process is based on a type of defective pixel indicated by the digital value for the particular pixel.
Ogino similarly teaches an apparatus (defect detecting correcting section, 208, figure 1) for processing pixel data output from a sensor (image pickup element, 203, paragraphs 0025 and 0026), wherein the pixel data includes a digital value indicating that a pixel is defective (“a defect flag 519 (1 bit) indicating whether or not a defect is formed” paragraph 0075).
However, Ogino additionally teaches that that the pixel data includes a first digital value indicating a first type of defective pixel and a second digital value indicating a second type of defective pixel (Ogino teaches that the pixel data includes “a black/white flag 520 (1 bit) for distinguishing between a white defect (white-spot defective pixel) and a black defect (black-spot defective pixel)” paragraph 0075. A 1-bit flag has first and second digital values (i.e. 0 and 1).), and wherein the defective pixel correction process is based on a type of defective pixel indicated by the digital value for the particular pixel (Defective pixel correction is performed by a defective pixel correcting section (2082, figures 1, 5 and 11), paragraphs 0026, 0033, 0035, 0036 and 0094-0098. The defective pixel correction by the defective pixel correcting section (2082) is performed according to a defect level (K), paragraphs 0094-0096, see figure 11. The defect level (K) is output by a selector (521, figure 5, paragraph 0093) and is based at least in part on the output of a threshold value determining circuit (515), figure 5, paragraph 0091. The output of the threshold value determining circuit (515) is calculated based on the type of defective pixel indicated by the black/white flag (520), see figure 5, paragraphs 0077 and 0080.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the one or more digital values taught by Sasai include a first digital value indicating a first type of defective pixel and a second digital value indicating a second type of defective pixel as taught by Ogino for the benefit of reducing adverse effects resulting from excessively correcting an output signal of a blinking defective pixel (Ogino, paragraph 0107).
Consider claim 9, and as applied to claim 8 above, Sasai does not explicitly teach the type of defective pixel.
Ogino teaches that the one or more digital values include a value 0 and a value 1 in the range from 0 to 2n -1, wherein the value of 0 indicates a first type of defective pixel, and wherein the value 1 indicates a second type of defective pixel (Ogino teaches that the pixel data includes “a black/white flag 520 (1 bit) for distinguishing between a white defect (white-spot defective pixel) and a black defect (black-spot defective pixel)” paragraph 0075. A 1-bit flag has first and second digital values (i.e. 0 and 1).).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the one or more digital values taught by Sasai include a first digital value indicating a first type of defective pixel and a second digital value indicating a second type of defective pixel as taught by Ogino for the benefit of reducing adverse effects resulting from excessively correcting an output signal of a blinking defective pixel (Ogino, paragraph 0107).
Consider claim 13, and as applied to claim 8 above, Sasai further teaches that the defective pixel correction process comprises an interpolation process using digital values of neighboring pixels to the particular pixel (see column 5, lines 44-61 and column 6, lines 24-36).
Consider claim 14, Sasai teaches:
An apparatus for processing pixel data (image processing apparatus, 10, figure 1), the apparatus comprising:
a sensor configured to capture pixel data (“an image sensor such as a CCD”, column 3, lines 50-52) comprising a plurality of pixel values ((“and 6, an interpolation processing unit for reading out replacement information-added image data 5 stored in the buffer unit 4”, column 4, lines 5-7) comprising a plurality of pixel values (see figure 2C, column 4, lines 49-56)), wherein each pixel value of the pixel data is represented by an original digital value in a range from 0 to 2n -1 (see D0-Dk and Dd in figure 2C), and wherein the original digital value indicates a light intensity value (The values D0-Dk (23) indicate a light intensity value, column 4, lines 49-56, column 4, lines 18-28, column 3, lines 50-54.); and
processing circuitry (replacement unit, 2, buffer unit, 4, figure 1) in communication with the sensor (see figure 1, column 3, line 49 through column 4, line 5), the processing circuitry configured to:
receive the pixel data (see column 3, lines 49-58);
identify one or more pixels in the pixel data as being defective pixels (i.e. based on defect information 1D, column 3, lines 60 and 61);
encode the pixel data to form encoded pixel data that identifies the defective pixels (see D0-Dk and Dd in figure 2C, column 4, lines 49-56), wherein one or more digital values of the encoded pixel data in the range from 0 to 2n -1 indicate a defective pixel (The digital value Dd (1D) indicates a defective pixel, column 4, lines 40-56.), wherein remaining values of the encoded pixel data in the range from 0 to 2n -1 indicate a light intensity value (The remaining values D0-Dk (23) indicate a light intensity value, column 4, lines 49-56, column 4, lines 18-28, column 3, lines 50-54.); and
send the encoded pixel data to an image signal processor (i.e. to interpolation processing unit 6, column 3, line 59 through column 4, line 17).
However, Sasai does not explicitly teach that the one or more digital values include a first digital value indicating a first type of defective pixel and a second digital value indicating a second type of defective pixel.
Ogino similarly teaches an apparatus (defect detecting correcting section, 208, figure 1) for processing pixel data output from a sensor (image pickup element, 203, paragraphs 0025 and 0026), wherein the pixel data includes a digital value indicating that a pixel is defective (“a defect flag 519 (1 bit) indicating whether or not a defect is formed” paragraph 0075).
However, Ogino additionally teaches that that the pixel data includes a first digital value indicating a first type of defective pixel and a second digital value indicating a second type of defective pixel (Ogino teaches that the pixel data includes “a black/white flag 520 (1 bit) for distinguishing between a white defect (white-spot defective pixel) and a black defect (black-spot defective pixel)” paragraph 0075. A 1-bit flag has first and second digital values (i.e. 0 and 1).).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the one or more digital values taught by Sasai include a first digital value indicating a first type of defective pixel and a second digital value indicating a second type of defective pixel as taught by Ogino for the benefit of reducing adverse effects resulting from excessively correcting an output signal of a blinking defective pixel (Ogino, paragraph 0107).
Consider claim 15, and as applied to claim 14 above, Sasai does not explicitly teach the type of defective pixel.
Ogino teaches that the one or more digital values include a value 0 and a value 1 in the range from 0 to 2n -1, wherein the value of 0 indicates a first type of defective pixel, and wherein the value 1 indicates a second type of defective pixel (Ogino teaches that the pixel data includes “a black/white flag 520 (1 bit) for distinguishing between a white defect (white-spot defective pixel) and a black defect (black-spot defective pixel)” paragraph 0075. A 1-bit flag has first and second digital values (i.e. 0 and 1).).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the one or more digital values taught by Sasai include a first digital value indicating a first type of defective pixel and a second digital value indicating a second type of defective pixel as taught by Ogino for the benefit of reducing adverse effects resulting from excessively correcting an output signal of a blinking defective pixel (Ogino, paragraph 0107).
Consider claim 18, and as applied to claim 14 above, Sasai further teaches that the apparatus (figure 1) further comprises the image signal processor (interpolation processing unit, 6, figure 1, column 4, lines 5-17).
Consider claim 19, and as applied to claim 18 above, Sasai further teaches that the image signal processor is configured to: perform a defective pixel correction process on a particular pixel based on the particular pixel being determined to be defective based on the encoded pixel data (“and 6, an interpolation processing unit for reading out replacement information-added image data 5 stored in the buffer unit 4, generating, by interpolation processing, pixel values representing all color information levels for a corresponding interpolation point from the pixel values of a plurality of pixels falling within a predetermined pixel region, and when pixel values used for interpolation processing includes a pixel value whose replacement information represents replacement, performing interpolation processing using an arithmetic expression different from a normal one, and outputting each obtained pixel value as the new image data 9” column 4, lines 5-17).
Sasai does not explicitly teach that the pixel correction is further based on the type of defective pixel indicated by the encoded pixel data.
Ogino additionally teaches that that the pixel data includes a first digital value indicating a first type of defective pixel and a second digital value indicating a second type of defective pixel (Ogino teaches that the pixel data includes “a black/white flag 520 (1 bit) for distinguishing between a white defect (white-spot defective pixel) and a black defect (black-spot defective pixel)” paragraph 0075. A 1-bit flag has first and second digital values (i.e. 0 and 1).), and wherein the defective pixel correction process is based on a type of defective pixel indicated by the digital value for the particular pixel (Defective pixel correction is performed by a defective pixel correcting section (2082, figures 1, 5 and 11), paragraphs 0026, 0033, 0035, 0036 and 0094-0098. The defective pixel correction by the defective pixel correcting section (2082) is performed according to a defect level (K), paragraphs 0094-0096, see figure 11. The defect level (K) is output by a selector (521, figure 5, paragraph 0093) and is based at least in part on the output of a threshold value determining circuit (515), figure 5, paragraph 0091. The output of the threshold value determining circuit (515) is calculated based on the type of defective pixel indicated by the black/white flag (520), see figure 5, paragraphs 0077 and 0080.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the pixel correction process taught by Sasai be performed according to the type of defective pixel as taught by Ogino for the benefit of reducing adverse effects resulting from excessively correcting an output signal of a blinking defective pixel (Ogino, paragraph 0107).
Consider claim 20, and as applied to claim 19 above, Sasai further teaches that the defective pixel correction process comprises an interpolation process using digital values of neighboring pixels to the particular pixel (see column 5, lines 44-61 and column 6, lines 24-36).
Claims 3, 10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sasai (US 6,977,681) in view of Ogino (US 2011/0080505), as applied to claims 2, 9 and 15 above, and further in view of Lee et al. (US 2024/0323559).
Consider claims 3, 10 and 16, and as applied to claims 2, 9 and 15 above, the combination of Sasai and Ogino does not explicitly teach that the first type of defective pixel is a single defect and the second type of defective pixel is a cluster defect.
Lee et al. similarly teaches a flag comprising a plurality of bits indicating a defective pixel (see paragraph 0063).
However, Lee et al. additionally teaches that the first type of defective pixel is a single defect and the second type of defective pixel is a cluster defect (“The location information di may also include an identification factor for identifying whether the defective pixel DP is the cluster of defective pixels CDP or the isolated defective pixel IDP.” Paragraph 0063).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first and second types of defective pixels taught by the combination of Sasai and Ogino be a single defect and a cluster defect, respectively, as taught by Lee et al. for the benefit of improving the performance of correcting defective pixels (Lee et al., paragraph 0006).
Claims 4, 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sasai (US 6,977,681) in view of Ogino (US 2011/0080505), as applied to claims 1, 8 and 14 above, and further in view of Hosono et al. (US 2020/0045256).
Consider claims 4, 11 and 17, and as applied to claims 1, 8 and 14 above, the combination of Sasai and Ogino does not explicitly teach that the one or more digital values include three or more values in the range from 0 to 2n-1, wherein the three or more values indicate three or more different types of defective pixels.
Hosono et al. similarly teaches using multiple bits to indicate defective pixel data (see “attribute”, figure 3, paragraphs 0074 and 0078).
However, Hosono et al. additionally teaches that the one or more digital values include three or more values in the range from 0 to 2n-1, wherein the three or more values indicate three or more different types of defective pixels (As shown in figure 10, the attribute values indicate at least 8 different types of defective pixels, paragraphs 0097 and 0098.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the one or more digital values taught by the combination of Sasai and Ogino include three or more values indicating three or more different types of defective pixels as taught by Hosono et al. for the benefit of enabling an order of defective pixel correction to be desirably set based upon the type of defective pixel and shooting condition (Hosono et al., paragraph 0236).
Prior Art
Consider claim 21, the prior art of record does not teach nor reasonably suggest that the defective pixel correction process comprises a first correction algorithm for the first type of defective pixel and a second, different correction algorithm for the second type of defective pixel, in combination with the other elements recited in parent claim 1.
Consider claim 22, the prior art of record does not teach nor reasonably suggest that the defective pixel correction process comprises a first correction algorithm for the first type of defective pixel and a second, different correction algorithm for the second type of defective pixel, in combination with the other elements recited in parent claim 8.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637