DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Applicant’s claim for the benefit of a prior-filed application under 63/464,347 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
All claims are examined with an effective filing date of May 5, 2023.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
MPEP § 2111.04(II) provides “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B.”
Claim 20 recites a method claim and must therefore any contingent limitations must be addressed.
Claim 20 recites
receiving a second command to access a second memory cell of the bank at least partially concurrently with accessing the active segment;
determining, based at least in part on receiving the second command to access the second memory cell, whether the second memory cell is associated with the active segment or one or more inaccessible segments of the bank, wherein the one or more inaccessible segments are inaccessible while the active segment is being accessed; and
accessing the second memory cell based at least in part on determining that the second memory cell is associated with an accessible segment of the bank different than the active segment and the one or more inaccessible segments.
The determining limitation is required within the broadest reasonable interpretation of the claim, as the reception of the second command is required. However, the determining limitation does not recite what result is required within performance of the claim, and therefore the condition for the accessing limitation (i.e. – the second memory cell is associated with an accessible segment) is not required within the broadest reasonable interpretation of the claim, and therefore the accessing is not required within the broadest reasonable interpretation of the claim.
For contrast, claims 1 and 14 require this limitation, as MPEP § 2111.04(II) provides that “The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6, 8, 10-12, 14-17, and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Mirichigni et al. (US 2021/0020213).
Regarding claim 1, Mirichigni teaches an apparatus (Fig. 1), comprising:
a bank of memory cells comprising a plurality of segments (Fig. 1, memory device 110 showing memory dies with memory arrays, Fig. 2 shows each memory die with a plurality of memory cells, and Fig. 3 shows the memory device in another manner, showing multiple banks 330, where the banks also comprise subarrays 335, see also [0068]); and
a controller coupled with the bank of memory cells (Fig. 1, memory controller 105, also seen in Fig. 3 element 315) and configured to cause the apparatus to:
receive a first command to access a first memory cell of the bank of memory cells (“In some examples, the host device may transmit multiple activation commands to the memory device 110 (e.g., via the external memory controller 105). For instance, the host device may determine to access one or more rows of memory cells within the memory device 110 (e.g., within the same or different subarrays of the memory device 110, within the same or different banks of the memory device 110) and may transmit an activation command to access a first row of memory cells and a second activation command to access a second row of memory cells. The first and second rows may be in a same bank, and the host device may determine a time to transmit the second activation command based on whether the first and second rows of memory cells are also in the same subarray or are in different subarrays of the bank,” [0021]);
access an active segment of the bank that is associated with the first memory cell based at least in part on receiving the first command (“In some examples, the external memory controller may send an activation command to the memory device 110 to open a row of memory cells in a subarray followed by an access command to access the row of memory cells in the subarray,” [0038]);
receive a second command to access a second memory cell of the bank at least partially concurrently with accessing the active segment (“In some examples, the host device may transmit multiple activation commands to the memory device 110 (e.g., via the external memory controller 105). For instance, the host device may determine to access one or more rows of memory cells within the memory device 110 (e.g., within the same or different subarrays of the memory device 110, within the same or different banks of the memory device 110) and may transmit an activation command to access a first row of memory cells and a second activation command to access a second row of memory cells. The first and second rows may be in a same bank, and the host device may determine a time to transmit the second activation command based on whether the first and second rows of memory cells are also in the same subarray or are in different subarrays of the bank,” [0021]; where tRP_S is utilized to represent a shorted row precharge time and indicate that this is before the precharge operation of the first row is complete, see [0016,0057], teaching that the second memory cell is accessed at least partially concurrently with access of the first row);
determine, based at least in part on receiving the second command to access the second memory cell, whether the second memory cell is associated with the active segment or one or more inaccessible segments of the bank, wherein the one or more inaccessible segments are inaccessible while the active segment is being accessed (“In some examples, the host device may transmit multiple activation commands to the memory device 110 (e.g., via the external memory controller 105). For instance, the host device may determine to access one or more rows of memory cells within the memory device 110 (e.g., within the same or different subarrays of the memory device 110, within the same or different banks of the memory device 110) and may transmit an activation command to access a first row of memory cells and a second activation command to access a second row of memory cells. The first and second rows may be in a same bank, and the host device may determine a time to transmit the second activation command based on whether the first and second rows of memory cells are also in the same subarray or are in different subarrays of the bank,” [0021]; cells in the same subarray as the first command are considered inaccessible because “In some cases, however, because each subarray may be associated with one corresponding latching circuit, phases associated with two rows in the same subarray may not be concurrently maintained by the latching circuitry. In such instances, an activation signal for a second row in the same subarray may be received after completion of a precharge operation of a first row in the same subarray (e.g., using a default row precharge time (tRP), which may be longer than tRP_S),” [0016], teaching that cells that utilize the same latching circuitry as the first command are inaccessible); and
access the second memory cell based at least in part on determining that the second memory cell is associated with an accessible segment of the bank different than the active segment and the one or more inaccessible segments (“The external memory controller 105 may determine to access a second row of memory cells (e.g., in a same or different subarray) and may select a time for sending a second activation command to the memory device 110 based on a tRP or a tRP_S, each of which may correspond to a delay (e.g., a time duration to wait) between a precharge command for the first row and the second activation command. For instance, the external memory controller 105 may determine to send the second activation command to open a second row of memory cells following a precharge command for a first row of memory cells according to the tRP_S if the second row of memory cells is in a different subarray than the first row of memory cells,” [0038], where tRP_S is utilized to represent a shorted row precharge time and indicate that this is before the precharge operation of the first row is complete, see [0016,0057], teaching that the second memory cell is accessed at least partially concurrently with access of the first row).
Regarding claim 2, Mirichigni teaches the apparatus of claim 1, and wherein the controller is further configured to cause the apparatus to:
receive a third command to access a third memory cell of the bank, wherein the third memory cell is associated with the one or more inaccessible segments “In some examples, the host device may transmit multiple activation commands to the memory device 110 (e.g., via the external memory controller 105). For instance, the host device may determine to access one or more rows of memory cells within the memory device 110 (e.g., within the same or different subarrays of the memory device 110, within the same or different banks of the memory device 110) and may transmit an activation command to access a first row of memory cells and a second activation command to access a second row of memory cells. The first and second rows may be in a same bank, and the host device may determine a time to transmit the second activation command based on whether the first and second rows of memory cells are also in the same subarray or are in different subarrays of the bank,” [0021]; while provided in the context of the first and second commands, Mirichigni’s discussion would necessarily apply to any future reception of commands as well;
determine whether accessing the third memory cell occurs at least partially concurrently with accessing the second memory cell (“In some examples, the host device may transmit multiple activation commands to the memory device 110 (e.g., via the external memory controller 105). For instance, the host device may determine to access one or more rows of memory cells within the memory device 110 (e.g., within the same or different subarrays of the memory device 110, within the same or different banks of the memory device 110) and may transmit an activation command to access a first row of memory cells and a second activation command to access a second row of memory cells. The first and second rows may be in a same bank, and the host device may determine a time to transmit the second activation command based on whether the first and second rows of memory cells are also in the same subarray or are in different subarrays of the bank,” [0021]);
determine whether the third memory cell is associated with the active segment or the one or more inaccessible segments (“In some examples, the host device may transmit multiple activation commands to the memory device 110 (e.g., via the external memory controller 105). For instance, the host device may determine to access one or more rows of memory cells within the memory device 110 (e.g., within the same or different subarrays of the memory device 110, within the same or different banks of the memory device 110) and may transmit an activation command to access a first row of memory cells and a second activation command to access a second row of memory cells. The first and second rows may be in a same bank, and the host device may determine a time to transmit the second activation command based on whether the first and second rows of memory cells are also in the same subarray or are in different subarrays of the bank,” [0021]; cells in the same subarray as the first command are considered inaccessible because “In some cases, however, because each subarray may be associated with one corresponding latching circuit, phases associated with two rows in the same subarray may not be concurrently maintained by the latching circuitry. In such instances, an activation signal for a second row in the same subarray may be received after completion of a precharge operation of a first row in the same subarray (e.g., using a default row precharge time (tRP), which may be longer than tRP_S),” [0016], teaching that cells that utilize the same latching circuitry as the first command are inaccessible); and
refrain from accessing the third memory cell concurrently with accessing the second memory cell based at least in part on determining that accessing the third memory cell occurs at least partially concurrently with accessing the second memory cell and determining that the third memory cell is associated with the one or more inaccessible segments (“Access to a second row of memory cells 205 within the same subarray may be performed through an activation command after a first delay (e.g., corresponding to tRP) following a precharge command,” [0057], “Time tRP 570 (e.g., Row-Precharge time) may be the time elapsed (e.g., a number of clock cycles, which may be the minimum number of clock cycles) between the memory device receiving precharge command 525-a and completion of the precharge operation of the open row inside first subarray 505. Thus, tRP 570 may be or include the time for the internal operations governed by precharge phases 555 to close the row inside first subarray 505,” [0096], teaching that when commands are received directed to the same subarray, i.e. a currently inaccessible segment, then the command is delayed so that it is not performed concurrently with a previous command).
Regarding claim 3, Mirichigni teaches the apparatus of claim 2, wherein the controller is further configured to cause the apparatus to:
transmit an indication that the third memory cell is prohibited for access based at least in part on determining that accessing the third memory cell occurs at least partially concurrently with accessing the second memory cell and determining that the third memory cell is associated with the one or more inaccessible segments (“The external memory controller 105 may determine to access a second row of memory cells (e.g., in a same or different subarray) and may select a time for sending a second activation command to the memory device 110 based on a tRP or a tRP_S, each of which may correspond to a delay (e.g., a time duration to wait) between a precharge command for the first row and the second activation command,” [0038], where sending the command with the tRP delay shows that the third memory cell is prohibited from access concurrently with the second memory cell).
Regarding claim 6, Mirichigni teaches the apparatus of claim 1, wherein the controller is further configured to cause the apparatus to:
transmit an indication that the second memory cell is permitted for access based at least in part on determining that the second memory cell is associated with the accessible segment (“The external memory controller 105 may determine to access a second row of memory cells (e.g., in a same or different subarray) and may select a time for sending a second activation command to the memory device 110 based on a tRP or a tRP_S, each of which may correspond to a delay (e.g., a time duration to wait) between a precharge command for the first row and the second activation command,” [0038], where sending the command for access with tRP_S corresponds to accessing the second memory cell with the accessible segments).
Regarding claim 8, Mirichigni teaches the apparatus of claim 1, and further teaches wherein the first command and the second command are activate commands (“In some examples, the external memory controller may send an activation command to the memory device 110 to open a row of memory cells in a subarray followed by an access command to access the row of memory cells in the subarray. The external memory controller 105 may determine to access a second row of memory cells (e.g., in a same or different subarray) and may select a time for sending a second activation command to the memory device 110 based on a tRP or a tRP_S, each of which may correspond to a delay (e.g., a time duration to wait) between a precharge command for the first row and the second activation command”, [0038], see also Fig. 5 showing the activation commands sent over the command bus CA bus depicted in Fig. 3).
Regarding claim 10, Mirichigni teaches the apparatus of claim1, and further teaches wherein each segment of memory cells is associated with a respective digit line of the bank of memory cells (Fig. 2, the columns of each grouping of memory cells is associated with a digit line).
Regarding claim 11, Mirichigni teaches the apparatus of claim 1, wherein the bank of memory cells comprise dynamic random access memory cells (Fig. 2 shows a memory cell with a DRAM architecture, see also “A memory cell 205 may store a charge representative of the programmable states in a capacitor. DRAM architectures may include a capacitor that includes a dielectric material to store a charge representative of the programmable state,” [0051]).
Regarding claim 12, Mirichigni teaches the apparatus of claim 1, wherein:
accessing the second memory cell comprises accessing the accessible segment associated with the second memory cell (“In some examples, the host device may transmit multiple activation commands to the memory device 110 (e.g., via the external memory controller 105). For instance, the host device may determine to access one or more rows of memory cells within the memory device 110 (e.g., within the same or different subarrays of the memory device 110, within the same or different banks of the memory device 110) and may transmit an activation command to access a first row of memory cells and a second activation command to access a second row of memory cells. The first and second rows may be in a same bank, and the host device may determine a time to transmit the second activation command based on whether the first and second rows of memory cells are also in the same subarray or are in different subarrays of the bank,” [0021], teaching that the second row is within the different subarray), and
accessing the accessible segment comprises accessing a word line of the bank of memory cells and a digit line associated with the accessible segment (Fig. 2 shows that accessing memory cells includes accessing a particular word line for the row address and a digit line for the column address).
Regarding claim 14, Mirichigni teaches a non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor (see [0139,0168]) to perform the functional limitations of the controller of claim 1 and can be rejected according to the same rationale.
Claims 15, 16, and 17 are rejected according to the same rationale of claims 2, 3, 6, respectively.
Claim 20 recites a method identical to the functional limitations of the controller of claim 1 and can be rejected according to the same rationale. For clarity of record, examiner finds that the rationale of claim 1 sufficient to teach all of claim 20’s limitations, even the limitation not required within the broadest reasonable interpretation of the claim, as discussed in the claim interpretation section.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4, 7, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Mirichigni in view of Andre et al. (US 2017/0315920).
Regarding claim 4, Mirichigni teaches the apparatus of claim 2, but fails to teach wherein refraining from accessing the third memory cell is configured to cause the apparatus to:
refrain from accessing the third memory cell until after a write back operation on the second memory cell has been completed.
Andre’s disclosure relates to memory access, and as such comprises analogous art.
Andre provides that “A “page” of memory cells is understood to be a grouping of memory cells that are accessed together as a unit. In some instances, a “page” may constitute a “row” of memory cells. Opening a page moves the data for the page from the array of memory cells into a cache or other form of temporary storage where the data is more readily accessed. Once the page is activated (opened), read and write operations to the page can be performed. Upon completion of the read/write operations for the open page, the page is closed. When a page is closed, the array is returned to a state ready for a subsequent page activation, and the data in the closed page cannot be accessed again for reads and writes without re-opening the page. In some memory devices, data moved to temporary storage during the activate command is immediately written back to the array, and, in some cases, data corresponding to write operations performed while the page is opened is also immediately written to the memory cells in the array. In such memory devices, a precharge operation may only precharge the bit lines and de-assert the word line corresponding to the page. In other memory devices, data moved to temporary storage during an activate and data written to the open page is not stored into the array until just prior to closing the page. As such, in those memory devices, the precharge operation would also including performing the write-back of data from temporary storage to the array. By waiting until just prior to closing the page to write the data back to the array, a memory device can save power or improve timing specifications associated with the moving or modifying of the data,” [0015].
Andre provides that in the prior art, “in some instances sequential accesses may be to a different page in the same bank. In the example shown, BANK1 PAGE1 is activated at block 210, and after read access time 211, read data 212 is output. If the next access is a read to BANK1 PAGE2, then PAGE1 of BANK1 must be closed via precharge 213 before PAGE2 of BANK1 can be opened via activate 220. Following the activate 220, read data 222 is not output until after read access time 221. Precharge 223 then closes PAGE2 of BANK1. As is apparent from FIG. 2, such back-to-back accesses to the same bank do not allow the time associated with the activate, read access time, and the precharge to be fully hidden. It may be possible to begin the precharge operation as the last of the read data is output (i.e. slightly before the completion of the read data block 212), but, as is shown, the time delay between read data output 212 from the first page and the read data output 222 from the second page is significant,” [0020].
An obvious combination can be identified: combining Andre’s disclosure of a write-back as part of the precharge operation, and in particular how the timing of activation waits for the precharge, including the write back, to be completed. Such a modification reads upon the limitation of the claim, as waiting for the tRP period in Mirichigni must necessarily also include the time for write-back, as the write-back is part of the precharge operation. Given the third command’s use of tRP (see the claim 2 rationale), then the refraining of the third command includes waiting for the write-back to be complete.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine Andre’s disclosure of a writeback part of the precharge operation with Mirichigni’s DRAM system. Both references are available as prior art, and as Andre provides additional detail to the precharge operation of the DRAM system, namely that precharge includes write-back, then the combination provides a predictable result: where Mirichigni’s system still operates, but one of ordinary skill in the art recognizes that the precharge operation discussed still includes a write-back operation.
Regarding claim 7, Mirichigni teaches the apparatus of claim 1, but fails to teach wherein accessing the first memory cell comprises performing a write-back operation on the first memory cell after reading the first memory cell.
Andre provides that “A “page” of memory cells is understood to be a grouping of memory cells that are accessed together as a unit. In some instances, a “page” may constitute a “row” of memory cells. Opening a page moves the data for the page from the array of memory cells into a cache or other form of temporary storage where the data is more readily accessed. Once the page is activated (opened), read and write operations to the page can be performed. Upon completion of the read/write operations for the open page, the page is closed. When a page is closed, the array is returned to a state ready for a subsequent page activation, and the data in the closed page cannot be accessed again for reads and writes without re-opening the page. In some memory devices, data moved to temporary storage during the activate command is immediately written back to the array, and, in some cases, data corresponding to write operations performed while the page is opened is also immediately written to the memory cells in the array. In such memory devices, a precharge operation may only precharge the bit lines and de-assert the word line corresponding to the page. In other memory devices, data moved to temporary storage during an activate and data written to the open page is not stored into the array until just prior to closing the page. As such, in those memory devices, the precharge operation would also including performing the write-back of data from temporary storage to the array. By waiting until just prior to closing the page to write the data back to the array, a memory device can save power or improve timing specifications associated with the moving or modifying of the data,” [0015].
Andre provides that in the prior art, “in some instances sequential accesses may be to a different page in the same bank. In the example shown, BANK1 PAGE1 is activated at block 210, and after read access time 211, read data 212 is output. If the next access is a read to BANK1 PAGE2, then PAGE1 of BANK1 must be closed via precharge 213 before PAGE2 of BANK1 can be opened via activate 220. Following the activate 220, read data 222 is not output until after read access time 221. Precharge 223 then closes PAGE2 of BANK1. As is apparent from FIG. 2, such back-to-back accesses to the same bank do not allow the time associated with the activate, read access time, and the precharge to be fully hidden. It may be possible to begin the precharge operation as the last of the read data is output (i.e. slightly before the completion of the read data block 212), but, as is shown, the time delay between read data output 212 from the first page and the read data output 222 from the second page is significant,” [0020].
An obvious combination can be identified: combining Andre’s disclosure of a write-back as part of the precharge operation, and in particular how the timing of activation waits for the precharge, including the write back, to be completed. Such a modification reads upon the limitation of the claim, as the combination now provides for a write-back as part of the operation of accessing a memory cell/page.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine Andre’s disclosure of a writeback part of the precharge operation with Mirichigni’s DRAM system. Both references are available as prior art, and as Andre provides additional detail to the precharge operation of the DRAM system, namely that precharge includes write-back, then the combination provides a predictable result: where Mirichigni’s system still operates, but one of ordinary skill in the art recognizes that the precharge operation discussed still includes a write-back operation.
Claim 18 is rejected according to the same rationale of claim 7.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Mirichigni in view of Ma et al. (US 2017/0153852).
Mirichigni teaches the apparatus of claim 2, but fails to teach wherein refraining from accessing the third memory cell is configured to cause the apparatus to:
discard the third command.
Ma’s disclosure relates to performing access to a multi-bank memory system and as such comprises analogous art.
As part of this disclosure, Ma provides that bank conflicts can occur when multiple access requests are directed to a same memory bank, and that when a packet is “If the packet is a first-type packet (e.g., a lossy packet) and bank confliction occurs, the first-type packet (or cells of the first-type packet) maybe dropped,” [0032], see also [0080].
An obvious modification can be identified: incorporating Ma’s ability to drop conflicting write packets when the write requests are lossy. Such a modification reads upon the limitation of the claim, as the third command has been interpreted to be directed to a non-accessible segment, i.e. in conflict with a previous command.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Ma’s ability to drop conflicting lossy requests into Mirichigni’s disclosure, as this avoids stalling the memory system with packets that are not strictly necessary due to their lossy nature but causing conflicts in accessing the memory.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Mirichigni in view of Chatterjee et al. (US 2017/0255552).
Mirichigni teaches the apparatus of claim 1, but fails to teach wherein the active segment and the one or more inaccessible segments share one or more respective sense components.
Chatterjee’s disclosure relates to providing subarrays/sub-channels within a memory bank and as such comprises analogous art.
As part of this disclosure, Chatterjee provides the ability to divide up banks into multiple subarrays and sub-channels, see Fig. 1B, where subarrays are linked via the same row decoder 115, see also [0030], and sub-channels are linked by the same sense amplifiers, see also [0032]. Chatterjee also discloses that “Each sub-channel 170 resembles an independent narrow channel. If a 256B row is activated in a sub-channel 170, another row can be activated in parallel in the same bank 120, but in a different sub-channel 170, as each sub-channel 170 has a dedicated I/O buffer 160 within the I/O buffer slice 125 that is not shared with another sub-channel 170,” [0046].
An obvious modification can be identified: incorporating Chatterjee’s disclosure of subarrays within sub-channels into Mirichigni’s disclosure. Such a modification reads upon the limitation of the claim, as Chatterjee provides that rows within the same sub-channel cannot be accessed simultaneously, where using Fig. 1B for example, if storage units 155-0Athrough 155-3A are accessed in subchannel 170-0 and subarray 180-A, then storage units 155-0B through 155-3B in subchannel 170-0 and subarray 180-B are still not accessible, despite being found in a different subarray/subchannel combination, due to sharing the same global sense amplifier circuitry.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Chatterjee’s subarray and subchannel circuitry into Mirichigni’s memory device, as the finer granularity of subarrays/subchannels in multiple dimensions provides for a lower energy cost of activation/access requests, see [0021].
Allowable Subject Matter
Claims 9 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 9 and 19 recite, using claim 9 for example language, wherein the controller is further configured to cause the apparatus to:
access a table comprising mappings between segments of memory cells and addresses of memory cells, wherein determining whether the second memory cell is associated with the active segment or the one or more inaccessible segments is based at least in part on accessing the table.
Mirichigni utilizes the column decoders to identify the subarrays, as does Chatterjee, with Chatterjee in particular utilizing a masking system to determine how to activate/not activate particular subchannels. Neither reference utilizes a mapping table between memory cell segments and memory cell addresses, let alone where the determining of the association with the active segment is based on the use of such a table.
While memory mapping tables are not novel in the art, and are even featured with individual cells, see Park et al. (US 10,083,764), the specific table recited is not seen in the art, nor does a reference provide a disclosure that would render such a feature obvious, leading to a determination of allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park, as cited above,
Lee (US 2015/0153966), Sumbul et al. (US 2019/0043560), Hush et al. (US 2019/0189189), Jacob et al. (US 2020/0278923), discloses processing access requests directed to different sub-banks/subarrays.
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/A.D.H./Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139