DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to amendment/reconsideration filed on 12/19/2025, the amendments have been considered. Claims 1, 2, 8, 9, and 14 have been amended. Claims 1-20 are pending for examination, the rejection cited as stated below.
Response to Arguments
Applicant's arguments filed 12/19/2025 have been fully considered but they are not persuasive. Applicant asserts that the prior art of Katragada fails to anticipate, teach, or suggest the amended portions of the claim language.
The Examiner respectfully disagrees, as Applicant has not provided any reasoning as to why the prior art of record fails to disclose the amended claim language. Merely stating that it does not teach the claims is not reason enough to suggest that the prior art of Katragada is silent to the teachings of the claims. However, the Examiner points to Katragada in various Paragraphs throughout the Specification, like Paragraph 0025, where there is a disclosure of isolated memory region (IMR) permission configuration registers are used in accordance to the techniques used, such as configuring a plurality of permission levels as needed. Paragraph 0029 discloses that configuration register values effectuating a configuration of multiple IMRs may be assigned during device power up, device enumeration, or other boot operations, such as prior to control being passed to an operating system of the device. Subregions are configured based on one or more memory address ranges and permission levels specified via configuration registers and allocated to each of the underlying integrated circuits (ICs) in accordance with the memory protection model. Paragraph 0054 discloses Isolated memory region (IMR) enforcement circuits are provided to protect isolated memory regions by allowing or preventing memory access requests from one of multiple distinct circuitry components based on values stored within configuration registers for the IMR enforcement circuits that specify memory address ranges and source permissions.
Based on the rationale explained above, the Examiner disagrees with the prior art being silent to the claimed embodiment.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8-12, and 14-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Aditya Katragada et al (US 20220283959 A1), hereinafter “Katragada”.
Regarding Claim 1, Katragada discloses a system on chip (Katragada, Paragraph 0014, e.g., disparately architected components within a single system, such as a system on chip (SoC)) comprising:
a memory controller, the memory controller (Katragada, Paragraph 0022, e.g., access control layer) configured to receive transactions containing transaction information (Katragada, Paragraph 0037, e.g., transaction type (such as code or data transaction types), transaction direction, and others) for an access to a memory (Katragada, Paragraph 0024, e.g., the memory access request is received, with the memory access request being associated with a target memory address and the ID of the source IC), store the transaction information in a command register (Katragada, Paragraph 0024, e.g., the target memory address is compared with a configurable memory address range identified via the Address_Min and Address_Max addresses stored respectively in IMR configuration registers 250 and 255), and control the access to the memory from the content of the command register (Katragada, Paragraph 0025, e.g., the source ID associated with the memory access request is compared with permission attributes specified via IMR permission configuration registers),
the memory controller comprising verification circuitry configured to determine the access to the memory depending on a comparison between the transaction information stored in the command register and a list of special information comprising special transactions and to receive a security level of the system on chip, the security level not being modifiable by software programing (Katragada, Paragraph 0025, e.g., if the target memory address specified by the received memory access request is within the memory address range identified via configuration registers, operations continue to operation 215. In operation 215, the source ID associated with the memory access request is compared with permission attributes specified via IMR permission configuration registers. Paragraph 0054 discloses Isolated memory region (IMR) enforcement circuits are provided to protect isolated memory regions by allowing or preventing memory access requests from one of multiple distinct circuitry components based on values stored within configuration registers for the IMR enforcement circuits that specify memory address ranges and source permissions).
Regarding Claim 2, Katragada discloses the system on chip of claim 1, wherein the verification circuitry is further configured to perform the determination of the access to the memory depending on the security level of the system on chip (Katragada, Paragraph 0025, e.g., a plurality of permission levels. The source ID associated with the memory access request is compared with permission attributes specified via IMR permission configuration registers).
Regarding Claim 3, Katragada discloses the system on chip of claim 2, wherein the list of special information comprising special transactions is created respectively for each possible security level of the system on chip (Katragada Paragraph 0029, e.g., Subregions may be configured based on one or more memory address ranges and permission levels specified via configuration registers (not separately depicted), and allocated to each of the underlying ICs in accordance with the memory protection model respectively expected by those ICs).
Regarding Claim 4, Katragada discloses the system on chip of claim 1, wherein the verification circuitry is configured to perform the determination so that the access is blocked if at least one item of the transaction information stored in the command register belongs to the list of special information, or if at least one item of the transaction information stored in the command register does not belong to the list of special information (Katragada, Paragraph 0026, e.g., In this manner, when target memory addresses are within the appropriate range and match security checks for that address range, cycles are allowed to proceed; non-matching cycles are dropped and error-responded when the target address is out of range or if the security attributes fail to match).
Regarding Claim 5, Katragada discloses the system on chip of claim 1, wherein the list of special information is established on at least one of the following types of transaction information: a pre-established command for an action in the memory; a memory region address; or a memory region size (Katragada, Paragraph 0024, e.g., the target memory address is compared with a configurable memory address).
Regarding Claim 6, Katragada discloses the system on chip of claim 1, wherein the verification circuitry is integrated directly internally into the memory controller (Katragada , Paragraph 0017, e.g., a single SOC or other integrated system may employ one or more IMR enforcement circuits (such as to enable the dynamic configuration of memory address ranges and permission levels for each of multiple IMRs)).
Regarding Claim 8, Katragada discloses a method for controlling a memory, the method comprising:
receiving, at a memory controller of a system on chip, transactions containing transaction information for a respective access to the memory (Katragada, Paragraph 0037, e.g., transaction type (such as code or data transaction types), transaction direction, and other);
receiving, at the memory controller, a security level of the system on chip, the security level being automatically modified as a boot process progresses (Katragada, Paragraph Paragraph 0029 discloses that configuration register values effectuating a configuration of multiple IMRs may be assigned during device power up, device enumeration, or other boot operations, such as prior to control being passed to an operating system of the device. Subregions are configured based on one or more memory address ranges and permission levels specified via configuration registers and allocated to each of the underlying integrated circuits (ICs) in accordance with the memory protection model. Paragraph 0054 discloses Isolated memory region (IMR) enforcement circuits are provided to protect isolated memory regions by allowing or preventing memory access requests from one of multiple distinct circuitry components based on values stored within configuration registers for the IMR enforcement circuits that specify memory address ranges and source permissions);
storing, at the memory controller, the transaction information received in a command register, the access to the memory being controlled from the content of the command register (Katragada, Paragraph 0024, e.g., the target memory address is compared with a configurable memory address range identified via the Address_Min and Address_Max addresses stored respectively in IMR configuration registers 250 and 255);
and determining, at the memory controller, the access to the memory depending on a comparison between the transaction information stored in the command register and a list of special information comprising special transactions (Katragada, Paragraph 0025, e.g., if the target memory address specified by the received memory access request is within the memory address range identified via configuration registers, operations continue to operation 215. In operation 215, the source ID associated with the memory access request is compared with permission attributes specified via IMR permission configuration registers. Paragraph 0054 discloses Isolated memory region (IMR) enforcement circuits are provided to protect isolated memory regions by allowing or preventing memory access requests from one of multiple distinct circuitry components based on values stored within configuration registers for the IMR enforcement circuits that specify memory address ranges and source permissions).
Regarding Claim 9, this claimed limitation is the same as the limitation addressed to Claim 2 above. Therefore, it is rejected under the same rationale.
Regarding Claim 10, this claimed limitation is the same as the limitation addressed to Claim 3 above. Therefore, it is rejected under the same rationale.
Regarding Claim 11 this claimed limitation is the same as the limitation addressed to Claim 4 above. Therefore, it is rejected under the same rationale.
Regarding Claim 12, this claimed limitation is the same as the limitation addressed to Claim 5 above. Therefore, it is rejected under the same rationale.
Regarding claim 14, Katragada discloses a system on chip (Katragada, Paragraph 0014, e.g., disparately architected components within a single system, such as a system on chip (SoC)) comprising:
a memory controller, the memory controller (Katragada , Paragraph 0022, e.g., access control layer) configured to:
receive transactions containing transaction information (Katragada, Paragraph 0037, e.g., transaction type (such as code or data transaction types) for an access to the memory controller or an access to a memory from a central processing unit (Katragada, Paragraph 0023, e.g., memory access request from a source IC), and to control the access to the memory using the transaction information, wherein controlling the access to the memory comprises blocking access to a memory region containing information for a boot process after the information has been used in the boot process (Katragada, Paragraph 0025, allow to or prevent from reading contents from memory locations associated with the IMR. Paragraph 0054, Isolated memory region (IMR) enforcement circuits may be provided to protect isolated memory regions by allowing or preventing memory access requests from one of multiple distinct circuitry components based on values stored within configuration registers for the IMR enforcement circuits that specify memory address ranges and source permissions. Paragraph 0056, The IMR enforcement circuit may further be to, responsive to a determination that the specified target address satisfies the defined address range and that the requesting one circuitry component is allowed to access the specified target address in the indicated manner, forward the memory access request for performance, and otherwise prevent the memory access request), the memory controller comprising verification circuitry configured to determine the access to the memory depending on a comparison between the transaction information and a list of special information comprising special transactions (Katragada, Paragraph 0025, e.g., if the target memory address specified by the received memory access request is within the memory address range identified via configuration registers, operations continue to operation 215. In operation 215, the source ID associated with the memory access request is compared with permission attributes specified via IMR permission configuration registers).
Regarding claim 15, Katragada discloses the system on chip of claim 14, wherein the verification circuitry is configured to receive a security level (Katragada, Paragraph 0025, e.g., a plurality of permission levels) of the system on chip and to perform the determination of the access to the memory depending on the security level of the system on chip (Katragada, Paragraph 0025, e.g., the source ID associated with the memory access request is compared with permission attributes specified via IMR permission configuration registers).
Regarding claim 16, Katragada discloses the system on chip of claim 15, wherein the list of special information comprising special transactions is created respectively for each possible security level of the system on chip (Katragada , Paragraph 0029, e.g., Subregions may be configured based on one or more memory address ranges and permission levels specified via configuration registers (not separately depicted), and allocated to each of the underlying ICs in accordance with the memory protection model respectively expected by those ICs).
Regarding claim 17, Katragada discloses the system on chip of claim 14, wherein the verification circuitry is configured to perform the determination so that the access is blocked if at least one item of the transaction information belongs to the list of special information, or if at least one item of the transaction information does not belong to the list of special information (Katragada, Paragraph 0026, e.g., In this manner, when target memory addresses are within the appropriate range and match security checks for that address range, cycles are allowed to proceed; non-matching cycles are dropped and error-responded when the target address is out of range or if the security attributes fail to match).
Regarding claim 18, Katragada discloses the system on chip of claim 14, wherein the list of special information is established on at least one of the following types of transaction information: a pre-established command for an action in the memory; a memory region address; or a memory region size (Katragada, Paragraph 0024, e.g., the target memory address is compared with a configurable memory address).
Regarding claim 19, Katragada discloses the system on chip of claim 14, wherein the verification circuitry is integrated directly internally into the memory controller (Katragada, Paragraph 0017, e.g., a single SOC or other integrated system may employ one or more IMR enforcement circuits (such as to enable the dynamic configuration of memory address ranges and permission levels for each of multiple IMRs)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Katragada in view of Edward Flanigan (US 20040250055 A1), hereinafter “Flanigan”.
Regarding claim 7, Katragada discloses the system on chip of claim 1, wherein each element of the list of special information comprises a pre-established command for an action in the memory (Katragada, Paragraph 0025, e.g., IMR permission configuration registers 260 (SecPerm_R, indicating one or more source IDs that are allowed to or prevented from reading the contents of memory locations associated with the IMR) and 265 (SecPerm_W, indicating one or more source IDs that are allowed to or prevented from writing to such memory locations)).
However, Katragada fails to explicitly disclose the pre-established commands being coded on 8 bits.
Flanigan, from the same or similar field of endeavor, discloses the pre-established commands being coded on 8 bits (Flanigan, Paragraph 0055, e.g., All or part of the eight bits of the 8-bit COMMAND register may be used to specify the command).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system on chip disclosed by Katragada to incorporate the command being coded on 8 bits disclosed by Flanigan. One of ordinary skill in the art would have been motivated to make this modification in order to maintain a more cost-effective design.
Regarding claim 13, Katragada discloses the method according to claim 8 above, wherein each element of the list of special information comprises a pre-established command for an action in the memory (Katragada, Paragraph 0025, e.g., IMR permission configuration registers 260 (SecPerm_R, indicating one or more source IDs that are allowed to or prevented from reading the contents of memory locations associated with the IMR) and 265 (SecPerm_W, indicating one or more source IDs that are allowed to or prevented from writing to such memory locations)).
However, Katragada fails to explicitly disclose the pre-established commands being coded on 8 bits.
Flanigan, from the same or similar field of endeavor, discloses the pre-established commands being coded on 8 bits (Flanigan, Paragraph 0055, e.g., All or part of the eight bits of the 8-bit COMMAND register may be used to specify the command).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system on chip disclosed by Katragada to incorporate the command being coded on 8 bits disclosed by Flanigan. One of ordinary skill in the art would have been motivated to make this modification in order to maintain a more cost-effective design.
Regarding claim 20, Katragada discloses the system on chip according to claim 14 above, where Katragada further discloses wherein each element of the list of special information comprises a pre-established command for an action in the memory (Katragada, Paragraph 0025, e.g., IMR permission configuration registers 260 (SecPerm_R, indicating one or more source IDs that are allowed to or prevented from reading the contents of memory locations associated with the IMR) and 265 (SecPerm_W, indicating one or more source IDs that are allowed to or prevented from writing to such memory locations)).
However, Katragada fails to explicitly disclose the pre-established commands being coded on 8 bits.
Flanigan, from the same or similar field of endeavor, discloses the pre-established commands being coded on 8 bits (Flanigan, Paragraph 0055, e.g., All or part of the eight bits of the 8-bit COMMAND register may be used to specify the command).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system on chip disclosed by Katragada to incorporate the command being coded on 8 bits disclosed by Flanigan. One of ordinary skill in the art would have been motivated to make this modification in order to maintain a more cost-effective design.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAVIER O GUZMAN whose telephone number is (571)270-0588. The examiner can normally be reached Monday - Friday 8 am to 4 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jorge L. Ortiz-Criado can be reached at (571)272-7624. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAVIER O GUZMAN/ Primary Examiner, Art Unit 2496
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