DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/652,700, application filed on 05/01/2024. Claims 1-20 are currently pending in this application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim(s) 1-3, 5-13 and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by KUO (US PG Pub No. 2024/0079308).
5. With respect to independent claim 1, KUO teaches:
a die package (semiconductor die package, see title, abstract; see package-on-package semiconductor package which contains two or more packages, para 2-3, 5-6) comprising:
a first memory device (see top package 400 of Fig 1A including a DRAM memory package, para 15); and
a system-on-a-chip (SoC) (see bottom package 300 of Fig 1A which is a SoC, para 15), comprising:
a first plurality of physical layer interfaces electrically connected to the first memory device (see conductive layer structures at interfaces, para 17; see SoC first semiconductor connected to first memory device in second third semiconductor device 400 using first interface, see para 5; see interface as distribution layers between first, second and third semiconductor devices, where second and third semiconductor devices can be memory devices, para 16-23),
wherein the SoC and the first memory device are in a first die package configuration (see first package-on-package configuration/assembly which includes the first semiconductor device as a SoC with a third semiconductor device 400 stacked above it which can be a memory device, para 15, 16-23); and
a second plurality of physical layer interfaces configured to electrically connect to a second memory device (see first semiconductor device SoC connected to second semiconductor device which can be a memory chip, and that connection is a second interface represented by interface distribution layers, Abstract, para 18-23),
wherein the SoC and the second memory device are in a second die package configuration (see first semiconductor SoC chip/package 102 sitting in a side-by-side configuration with the second memory semiconductor device 132, see Fig 1A and para 17).
6. With respect to independent claim 9, KUO teaches:
A die package comprising:
a first memory device (see top package 400 of Fig 1A including a DRAM memory package, para 15);
a second memory device (see second semiconductor device 132 of Fig 1A which can be a DRAM memory device, para 18); and
a system-on-a-chip (SoC) (see bottom package 300 of Fig 1A which is a SoC, para 15), the SoC comprising:
a first plurality of physical layer interfaces (see conductive layer structures at interfaces, para 17; ) electrically connected to the first memory device (see SoC first semiconductor connected to first memory device in second third semiconductor device 400 using first interface, see para 5; see interface as distribution layers between first, second and third semiconductor devices, where second and third semiconductor devices can be memory devices, para 16-23),
wherein the SoC and the first memory device are in a first die package configuration (see first package-on-package configuration/assembly which includes the first semiconductor device as a SoC with a third semiconductor device 400 stacked above it which can be a memory device, para 15, 16-23);
a second plurality of physical layer interfaces electrically connected to the second memory device (see first semiconductor device SoC connected to second semiconductor device which can be a memory chip, and that connection is a second interface represented by interface distribution layers, Abstract, para 18-23),
wherein the SoC and the second memory device are in a second die package configuration (see first semiconductor SoC chip/package 102 sitting in a side-by-side configuration with the second memory semiconductor device 132, see Fig 1A and para 17); and
at least one power rail configured to provide power to the first plurality of physical layer interfaces and the second plurality of physical layer interfaces (see single column and multi-column conductive structure for providing power and ground to data channels/interfaces to transfer data to/from the first, second and third semiconductor packages/devices, where each of the second and third semiconductor package can be a memory or a DRAM, para 34-36).
7. With respect to independent claim 16, KUO teaches:
a first plurality of physical layer interfaces configured to electrically connect to a first memory device when the SoC and the first memory device are in a first die package configuration (see conductive layer structures at interfaces, para 17; see SoC first semiconductor connected to first memory device in second third semiconductor device 400 using first interface, see para 5; see interface as distribution layers between first, second and third semiconductor devices, where second and third semiconductor devices can be memory devices, para 16-23; see first package-on-package configuration/assembly which includes the first semiconductor device as a SoC with a third semiconductor device 400 stacked above it which can be a memory device, para 15, 16-23);
a second plurality of physical layer interfaces configured to electrically connect to a second memory device when the SoC and the second memory device are in a second die package configuration (see first semiconductor device SoC connected to second semiconductor device which can be a memory chip, and that connection is a second interface represented by interface distribution layers, Abstract, para 18-23; see first semiconductor SoC chip/package 102 sitting in a side-by-side configuration with the second memory semiconductor device 132, see Fig 1A and para 17); and
a processor configured to generate and transmit power regulator data to a power control device, the power regulator data causing the power control device to enable power to at least one of the first plurality of physical layer interfaces and the second plurality of physical layer interfaces (see power management unit, para 18; see single column and multi-column conductive structure for providing power and ground to data channels/interfaces to transfer data to/from the first, second and third semiconductor packages/devices, where each of the second and third semiconductor package can be a memory or a DRAM, para 34-36).
8. With respect to claims 2, 10 and 17, KUO teaches:
wherein the first die package configuration is package-on-package (POP) (see PoP package with package on package vertical stacked orientation/configuration, para 15).
9. With respect to claims 3 and 11, KUO teaches:
wherein the first memory device is positioned on a top surface of the SoC (see third semiconductor chip which can be a memory is stacked on top of and connected to first semiconductor chip which is a SoC chip package, para 15-20).
10. With respect to claim 5, KUO teaches:
wherein the first plurality of physical layer interfaces comprise at least four physical layer interfaces (see four interfaces for memory access, for interfacing between SoC and four channels of memory, para 45).
11. With respect to claim 6, KUO teaches:
wherein the second plurality of physical layer interfaces comprise at least two physical layer interfaces (see two data channels for interfacing between SoC and two channels of memory, para 45, para 35).
12. With respect to claim 7, KUO teaches:
wherein the second plurality of physical layer interfaces are electrically connected to the second memory device (see two data channels for interfacing between SoC and two channels of memory, para 45, para 35; see first semiconductor device SoC connected to second semiconductor device which can be a memory chip, and that connection is a second interface represented by interface distribution layers, Abstract, para 18-23; see first semiconductor SoC chip/package 102 sitting in a side-by-side configuration with the second memory semiconductor device 132, see Fig 1A and para 17).
13. With respect to claims 8, 13 and 18, KUO teaches:
wherein the SoC is configured to:
transfer data with the first memory device using each of the first plurality of physical layer interfaces (see four interfaces for memory access, for interfacing between SoC and four channels of memory, para 45); and
transfer data with the second memory device using the second plurality of physical layer interfaces (see two data channels for interfacing between SoC and two channels of memory, para 45, para 35).
14. With respect to claims 12 and 19, KUO teaches:
wherein the first plurality of physical layer interfaces comprise at least four physical layer interfaces, and the second plurality of physical layer interfaces comprise at least two physical layer interfaces (see four interfaces for memory access, for interfacing between SoC and four channels of memory, para 45; see two data channels for interfacing between SoC and two channels of memory, para 45, para 35).
15. With respect to claim 20, KUO teaches:
at least one power rail configured to provide the power to the first plurality of physical layer interfaces and the second plurality of physical layer interfaces (see power management unit, para 18; see single column and multi-column conductive structure for providing power and ground to data channels/interfaces to transfer data to/from the first, second and third semiconductor packages/devices, where each of the second and third semiconductor package can be a memory or a DRAM, para 34-36).
Claim Rejections - 35 USC § 103
16. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
17. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over KUO (US PG Pub No. 2024/0079308) in view of OLLIVIER (US PG Pub No. 2019/0243961).
18. With respect to claim 4, KUO appears to be silent regarding:
wherein the second die package configuration is system-in-a-package (SiP).
However, OLLIVIER teaches:
wherein the second die package configuration is system-in-a-package (SiP) (see second die package 150 as a SiP connected to a PoP chipset which has an SoC and memory as part of the PoP package, Fig 1, para 79, 88-91).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Ollivier’s dual PoP and SiP packages into one multi-package arrangement for at least the following reason(s): OLLIVIER suggests that multi-package configurations like that taught by KUO and OLLIVIER can be advantageous in certain smaller compact products such as wearables, watches and phones where a significant amount of processing and memory power is required with lower power requirements, reduced latency, and compact reduced-wire designs.
Allowable Subject Matter
19. Claims 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
20. With respect to claims 14, the prior art made of record fails to teach the combination of steps recited in independent claim 14, including the following particular combination of steps as recited in claim 14, as follows:
a processor and a block head switch configured to allow the power on the at least one power rail, wherein the processor is configured to transmit a signal to the block head switch, and the block head switch is configured to allow the power on the at least one power rail based on the signal.
21. With respect to claims 15, the prior art made of record fails to teach the combination of steps recited in independent claim 15, including the following particular combination of steps as recited in claim 15, as follows:
a processor, a clock generator configured to generate a clock signal, and a gating circuit configured to provide the clock signal to at least one of:
the first plurality of physical layer interfaces and the second plurality of physical layer interfaces,
wherein: the processor is configured to transmit an enable signal to the gating circuit; and
the gating circuit is configured provide the clock signal based on the enable signal.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
