Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 recites the limitation "the surface of the epitaxial layer” which lacks antecedent basis. For examination purposes, “the surface of the epitaxial layer” is interpreted as “a surface of the epitaxial layer.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng (CN 107799592 A) in further view of Tominaga (US 20180323299 A1).
Regarding Claim 1, Zheng teaches a method of manufacturing a semiconductor device (see Fig. 2), comprising:
forming an epitaxial layer (11) on a substrate (10);
forming a hard mask layer (20, 25) on the epitaxial layer (shown Fig. 9), the hard mask layer having a first portion (25) and a second portion (20), with a gap between the first portion and the second portion (shown Fig. 9);
performing an oxidation process (shown Fig. 7) to form an oxide layer (23/24) on a surface of the hard mask layer (shown Figs. 7-9);
forming a source region (14) in the epitaxial layer through the gap of the hard mask layer (shown Fig. 9);
removing the first portion of the hard mask layer and the oxide layer (shown Fig. 10);
forming a well region (12) in the epitaxial layer using the second portion of the hard mask layer as an ion implantation mask (shown Fig. 5);
removing the second portion of the hard mask layer (shown Fig. 10);
forming a junction field effect transistor region (JFET, shown Fig. 2) in the epitaxial layer;
forming a dielectric layer (17) on the junction field effect transistor region; and
forming a gate structure (18) at a side of the dielectric layer (shown Fig. 2).
Zheng teaches that the junction field effect transistor (JFET) region is a portion of the n-type drift layer between p-base regions 12, but does not explicitly teach that the JFET regions is formed by:
forming a sacrificial dielectric layer on the source region and the well region;
forming a junction field effect transistor region in the epitaxial layer using the sacrificial dielectric layer as an ion implantation mask;
removing the sacrificial dielectric layer.
Tominaga teaches a method of manufacturing a semiconductor device having a “highly concentrated JFET region”, wherein an impurity concentration is “higher than that of the silicon carbide drift layer” (see Tominaga: Abstract).
The method of forming the JFET region of Tominaga comprises steps of forming a sacrificial dielectric layer (90e, see Tominaga: Figs. 2f and [0054]) on a source region (40) and a well region (30);
forming a junction field effect transistor region (22) in an epitaxial layer (20) using the sacrificial dielectric layer as an ion implantation mask (see [0054]); and
removing the sacrificial dielectric layer (see [0054] and Fig. 2(g)).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement the steps of Tominaga to the manufacturing method of Zheng as this would increase an impurity concentration of the JFET region such that “the p-n junction electric field intensity in the off-state under the same on condition can be reduced” and a “significant improvement in the reliability of the silicon carbide semiconductor device” is achieved (see also [0067] and [0073]).
Regarding Claim 2, Zheng as modified by Tominaga teaches the method of claim 1, wherein the well region comprises a channel region (Zheng: 15), and the channel region of the well region is adjacent to the source region (shown Fig. 2), and a thickness of the oxide layer (“0.3-4 microns”) is equal to a width of the channel region of the well region (“0.3-4 microns”).
Regarding Claim 8, Zheng as modified by Tominaga teaches the method of claim 1, wherein the oxidation process has a higher oxidation rate on the surface of the hard mask layer than on a surface of the epitaxial layer (shown Fig. 7), wherein at least a portion of a surface of the epitaxial layer is not oxidized (surface corresponding to JFET region).
Regarding Claim 10, Zheng as modified by Tominaga teaches the method of claim 1, further comprising:
performing an annealing process on the epitaxial layer before forming the gate structure (described “activation annealing” being performed prior to thermal oxidation of gate dielectric material layer 17).
Claim(s) 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng (CN 107799592 A) in view of Tominaga (US 20180323299 A1) in further view of Zinn (US 20150162431 A1).
Regarding Claim 3, Zhang as modified by Tominaga teaches the method of claim 2, wherein forming the gate structure at the side of the dielectric layer comprises:
forming a gate dielectric material layer (17) on the source region and the well region (shown Fig. 2);
forming a gate material layer (18) on the gate dielectric material layer;
the gate material layer being a gate on the channel region of the well region (shown Fig. 2).
Zheng and Tominaga do not explicitly teach forming the gate material layer on a dielectric layer distinct from the gate dielectric material layer and patterning the gate dielectric material layer using the gate as a mask to form a gate dielectric layer.
Zinn teaches a method of forming a split-gate structure (shown Fig. 2) wherein a gate material layer (209) is formed at a side of a dielectric layer (230, a “dielectric placeholder structure”) over a gate dielectric material layer (208, see Fig. 5(c)) and the gate dielectric material layer is subsequently patterned using the gate (210) as a mask (shown Fig. 5(d), wherein portions of 208 outside the gate are removed.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the gate structure of Zheng and Tominaga to be a split-gate structure as taught by Zinn as this would advantageously reduce a critical dimension of the gate structure (see Zinn: [0033]) while further reducing gate-to-drain overlap capacitance in the drain drift region when compared to a conventional structure (see Zinn: [0051]).
Specifically, this modification would teach steps of forming a gate dielectric material layer on the source region and the well region, forming a gate material layer on the gate dielectric material layer and the dielectric layer, removing a horizontal portion of the gate material layer (See Zinn: Figs. 5(c)-5(d)), leaving a vertical portion of the gate material layer to form a gate on the channel region of the well region; and
patterning the gate dielectric material layer using the gate as a mask to form a gate dielectric layer.
Regarding Claim 4, Zheng as modified by Tominaga and Zinn teaches the method of claim 3, wherein a width of the gate becomes wider as it approaches the epitaxial layer (as modified by Zinn, see Fig. 5(d)).
Regarding Claim 5, Zheng as modified by Tominaga and Zinn teaches the method of claim 3, wherein the gate has both a vertical sidewall and an arc-shaped sidewall (as modified by Zinn, see Fig. 5(d)).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Zheng (CN 107799592 A) in view of Tominaga (US 20180323299 A1) in further view of Ge et. al. (A Channel Self-Alignment Process for High-Voltage VDMOSFETs in 4H-SiC, 2021).
Regarding Claim 9, Zheng as modified by Tominaga teaches the method of claim 1. Zheng further teaches the hard mask layer being made of “a metal or metal oxide”.
Zheng and Tominaga do not explicitly teach a hard mask layer being made of polycrystalline silicon.
Ge teaches a method of forming a narrow channel feature in a VDMOSFET wherein an oxidized polysilicon mask is implemented to tune a width and alignment of channel regions in a well region (see Ge: Figure 2).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the mask material of Zheng to be polycrystalline silicon as suggested by Ge as this method “can better solve the problem of short channel generation” and ensures “consistency of the channel length on both sides of the cell” (see Ge: Conclusion), particularly as applied to SiC power devices.
Claim(s) 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zinn (US 20150162431 A1) in further view of Tominaga (US 20180323299 A1).
Regarding Claim 11, Zinn teaches a semiconductor device (200, shown Fig. 2), comprising:
an epitaxial layer (204), the epitaxial layer comprising:
a well region (214), the well region comprising a channel region (220, shown Fig. 4);
a source region (212), in the well region, wherein the channel region of the well region is adjacent to the source region (shown Fig. 4); and
a junction field effect transistor region (region between adjacent channel regions corresponding to d1, shown Fig. 4) adjacent to the well region (shown Fig. 4);
a dielectric layer (230), on the junction field effect transistor region (shown Fig. 4); and
a gate (210), adjacent to the dielectric layer and covering the channel region of the well region (shown Fig. 4), and a boundary of the gate being substantially aligned with a boundary between the junction field effect transistor region and the well region (shown Fig. 4, see also [0032] which describes a distance 222 being minimized such that a vertical wall of the gate structure and a vertical portion of the well region are substantially aligned).
Zinn does not explicitly teach a base region in the well region and the source region being adjacent to the base region.
Tominaga teaches a semiconductor device (see Fig. 1) analogous to that of Zinn wherein a well (30) comprises a base region (35) and a source region (40) and a JFET region (22) adjacent the well region (shown Fig. 1).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the well region of Zinn to further comprise a base region as suggested by Tominaga as this provides a well contact region to “obtain a favorable electrical contact” between the well region and a frontside electrode (i.e., a source electrode, see also Tominaga: [0053]).
Regarding Claim 12, Zinn as modified by Tominaga teaches the semiconductor device of claim 11, wherein a width of the gate becomes wider as it approaches the epitaxial layer (shown Fig. 4).
Regarding Claim 13, Zinn as modified by Tominaga teaches the semiconductor device of claim 11, wherein the gate has both a vertical sidewall and an arc-shaped sidewall (shown Fig. 4).
Regarding Claim 14, Zinn as modified by Tominaga teaches the semiconductor device of claim 13, wherein the vertical sidewall of the gate is in contact with the dielectric layer (shown Fig. 4).
Regarding Claim 15, Zinn as modified by Tominaga teaches the semiconductor device of claim 11, wherein a vertical projection of the gate on the epitaxial layer overlaps the junction field effect transistor region by a distance 222 (see [0032]).
Zinn further suggests that the overlap 222 can be “tuned to be only as narrow as required to ensure connectivity of the channel to the drain.”
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to further extend the dielectric placeholder structure such that a gate-to-bulk overlap is further reduced to zero and further reducing gate-to-bulk overlap capacitance (see also [0019] and [0032]) through routine optimization.
Specifically, this modification would teach that a vertical projection of the gate on the epitaxial layer does not overlap the junction field effect transistor region.
Regarding Claim 16, Zinn as modified by Tominaga teaches the device of claim 11. Zinn further teaches that the dielectric layer “has a thickness sufficient to block the self-align implant so that no P-type dopant penetrates” the dielectric layer, but is silent regarding a specific thickness of the dielectric layer (see [0028]).
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Zinn shows that a thickness of the dielectric layer is a result-effective variable because it reveals that sufficient thickness is required to block the self-align implant so that no p-type dopant can penetrate the dielectric layer (see [0028]).
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal thickness of the dielectric layer to minimize overall device thickness while ensuring a necessary thickness of the dielectric layer to block the self-align implant dopant.
Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
More specifically, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a dielectric layer at a thickness of 0.8 and 1 microns through routine optimization.
Regarding Claim 17, Zinn as modified by Tominaga teaches the semiconductor device of claim 11, further comprising a gate dielectric layer (208) between the gate and the well region (shown Fig. 2), and a thickness of the gate dielectric layer is less than a thickness of the dielectric layer (shown Fig. 2).
Regarding Claim 18, Zinn as modified by Tominaga teaches the semiconductor device of claim 17, wherein the gate dielectric layer is in contact with the dielectric layer (shown Fig. 2).
Regarding Claim 19, Zinn as modified by Tominaga teaches the semiconductor device of claim 11, wherein the source region and the junction field effect transistor region are of a first semiconductor type (n-type), and the base region and the well region may be of a second semiconductor type (p-type), and the first semiconductor type is different from the second semiconductor type.
Regarding Claim 20, Zinn as modified by Tominaga teaches the semiconductor device of claim 11, further comprising a drift region beneath the junction field effect transistor region.
Tominaga further teaches that an ion doping concentration of the junction field effect transistor region is greater than that of the drift region.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a higher impurity concentration of a JFET region as suggested by Tominaga such that “the p-n junction electric field intensity in the off-state under the same on condition can be reduced” and a “significant improvement in the reliability of the silicon carbide semiconductor device” is achieved (see also Tominaga: [0067] and [0073]).
Specifically, this modification would teach an ion doping concentration of the junction field effect region being greater than that of the drift region.
Allowable Subject Matter
Claims 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claims 6 and 7, Zheng as modified by Tominaga teaches that the sacrificial dielectric layer is formed after a second portion of a hard mask layer is removed and the dielectric layer is formed after the sacrificial dielectric layer is removed.
The prior art does not teach or suggest in any combination steps of forming the sacrificial dielectric layer to be in contact with the second portion of the hard mask layer as cited in claim 6 or forming the dielectric layer to be in contact with the sacrificial dielectric layer as cited in claim 7.
As such, claims 6 and 7 would be allowable over the prior art if rewritten in independent form.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Noguchi (US 20190229191 A1) teaches a device (100, see Fig. 1) comprising a substrate (1), an epitaxial region (2), a well region (4), a base region (5) and a source region (6), wherein an order of formation of the well region, base region and source region “may be arbitrary” (see [0073]) and multiple mask layers are implemented during their formation.
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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