DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-3, 5 and 8-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka Akira JP 2012216576 A (the ‘576 reference, of record and cited in a related PCT report), Semiconductor Device and Method of Forming the Same, Published November 08, 2012, the following rejections are based on an English translation by USPTO-PE2E.
The reference discloses in Fig. 1b, Reference-Signs-List/Description of Symbols (page 13) and other text a semiconductor device as claimed.
Referring to claim 1, the ‘576 reference discloses a semiconductor device comprising:
a chip (semiconductor substrate 2) that has a main surface;
a main surface electrode (3, 4) that covers the main surface;
pillar electrodes (7) that are arranged on the main surface electrode at an interval;
a sealing insulator (10) that covers a region between the pillar electrodes on the main surface electrode such as to expose parts (top surfaces) of the pillar electrodes (7); and
at least one terminal film (5, 6) that covers at least one of the pillar electrodes (7) on the sealing insulator (10).
Referring to claim 2, Fig. 1b depicts that the pillar electrodes (7) are each erected in a vertically long columnar shape in cross sectional view.
Referring to claim 3, Fig. 1b depicts that the terminal film (5, 6) is thinner than the pillar electrodes (7).
Referring to claim 5, Fig. 1b depicts that the pillar electrodes (7) are thicker than the main surface electrode (3, 4), and the sealing insulator (10) is thicker than the main surface electrode (3, 4).
Referring to claim 8, the reference further discloses that the pillar electrodes (7) each include a Cu-based metal (page 8, second full paragraph).
Referring to claim 9, the reference further discloses that the terminal film (surface second electrode 5, 6) includes [at least one among an Ag-based metal film, an Al-based metal film,] a Cu-based metal film (page 7, second paragraph), [an Ni-based metal film, a Pd-based metal film, and an Au-based metal film].
Referring to claim 10, the reference further discloses that the pillar electrodes (7) each have an electrode surface and an electrode side wall, and the sealing insulator (10) covers the pillar electrodes such as to expose the electrode surfaces and cover the electrode side walls.
Referring to claim 11, Fig. 1b depicts that the sealing insulator (10) has an insulating main surface that forms a single flat surface with the electrode surfaces of the pillar electrodes (7).
Referring to claim 12, Fig. 1b depicts that the chip (2) has a side surface, and the sealing insulator (10) has an insulating side wall that forms a single flat surface with the side surface.
3. Claims 1-5 and 8-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chew U.S. Patent Application Publication 2022/0102254 A1 (the ‘254 reference).
The reference discloses in Fig. 25 and other figures and related text a semiconductor device as claimed.
Referring to claim 1, the ‘254 reference discloses a semiconductor device comprising:
a chip (113, para [26] (paragraph(s) [0026])) that has a main surface (upper surface);
a main surface electrode (comprising pads 103, para [26], see Figs. 3b, 6b-6c) that covers the main surface;
pillar electrodes (127, best seen in Figs. 23a-23b, para [184]) that are arranged on the main surface electrode at an interval;
a sealing insulator (107/146, para [82, 186], see Figs. 6b, 11) that covers a region between the pillar electrodes (127) on the main surface electrode (103) such as to expose parts (top surfaces) of the pillar electrodes (127); and
at least one terminal film (131, para [193]) that covers at least one of the pillar electrodes (127) on the sealing insulator (107/146).
Referring to claim 2, Fig. 25 depicts that the pillar electrodes (127) are each erected in a vertically long columnar shape in cross sectional view.
Referring to claim 3, Fig. 25 depicts that the terminal film (131) is thinner than the pillar electrodes (127).
Referring to claim 4, Fig. 25 depicts that the terminal film (131) has a thickness of not more than ¼ the thickness of the pillar electrodes (127).
Referring to claim 5, Fig. 25 (and Fig. 3b) clearly depicts that the pillar electrodes (127) are thicker than the main surface electrode (103), and the sealing insulator (107/146) is thicker than the main surface electrode (103).
Referring to claim 8, the reference further discloses that the pillar electrodes (127) each include a Cu-based metal (“copper”, para [184]).
Referring to claim 9, the reference further discloses that the terminal film (131) includes at least one among an [Ag-based metal film, an Al-based metal film, a Cu-based metal film,] an Ni-based metal film, a Pd-based metal film, and an Au-based metal film (“nickel”, ”gold”, “palladium”, para [193]).
Referring to claim 10, the reference further discloses that the pillar electrodes (127) each have an electrode surface and an electrode side wall, and the sealing insulator (107/146) covers the pillar electrodes (127) such as to expose the electrode surfaces and cover the electrode side walls.
Referring to claim 11, Fig. 25 depicts that the sealing insulator (107/146) has an insulating main surface that forms a single flat surface with the electrode surfaces of the pillar electrodes (127).
Referring to claim 12, Fig. 25 depicts that the chip (113) has a side surface, and the sealing insulator (107/146) has an insulating side wall (that of 107) that forms a single flat surface with the side surface.
Referring to claim 13, the reference further discloses:
an insulating film (105, see Fig. 3b, para [26]) that partially covers the main surface electrode (103);
wherein the pillar electrodes (127) are arranged on the main surface electrode (103) (Figs. 3b, 23a, 23b, 25) at intervals from the insulating film.
Referring to claim 14, the reference further discloses that the sealing insulator (107/146) has a portion that covers the main surface electrode (103) across the insulating film (105) (best seen in Figs. 3b, 23a, 23b, 25).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4.1. Claim 4 is rejected under 35 U.S.C. §103 as being unpatentable over Tanaka Akira JP 2012216576 A (the ‘576 reference, of record and cited in a related PCT report).
Referring to claim 4, although the reference does not specifically disclose relative dimensions as claimed, the claimed relative dimensions (the terminal film has a thickness of not more than ¼ the thickness of the pillar electrodes) will not support the patentability of subject matter encompassed by the prior art (the ‘576 reference teaches that the sealing insulating (10, which has the same thickness as the pillar electrode 7) should be thick to reduce warpage, page 3, 4th paragraph, and, as depicted in Fig. 1b, the terminal film (5, 6) has a thickness smaller than that of the pillar electrode 7) unless there is evidence indicating such dimensions are critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation"; MPEP 2144.05.
4.2. Claim 16 is rejected under 35 U.S.C. §103 as being unpatentable over Tanaka Akira JP 2012216576 A (the ‘576 reference) in view of Mawatari U.S. Patent Application Publication 20120193778.
Referring to claim 16, the ‘576 reference discloses the sealing insulator (10) as detailed above for claim 1, but does not disclose that the sealing insulator includes a thermosetting resin.
Mawatari, in disclosing a semiconductor device comprising a sealing insulator (Fig. 4), discloses that the sealing insulator includes a thermosetting resin (paragraph(s) [0025]), thereby teaching that thermosetting resin is a material suitable for a sealing insulator.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s sealing insulator (10) utilizing a thermosetting resin. One would have been motivated to make such a modification in view of the teachings in Mawatari that thermosetting resin is a material suitable for a sealing insulator.
4.3. Claim 17-20 are rejected under 35 U.S.C. §103 as being unpatentable over Tanaka Akira JP 2012216576 A (the ‘576 reference) in view of Hiyoshi et al. U.S. Patent Application Publication 20160013137.
Referring to claim 20, the ‘576 reference discloses a chip (2) as detailed above for claim 1, but does not disclose that the chip includes a monocrystal of a wide bandgap semiconductor.
Hiyoshi, in disclosing a semiconductor device comprising a chip (10, Fig. 5), discloses that the chip includes a monocrystal of a wide bandgap semiconductor (paragraph(s) [0076]) for forming a semiconductor device with a high breakdown voltage and a low power consumption (paragraph(s) [0004]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s chip (2) utilizing a chip including a monocrystal of a wide bandgap semiconductor. One would have been motivated to make such a modification in view of the teachings in Hiyoshi for forming a semiconductor device with a high breakdown voltage and a low power consumption.
Thus, such a modification would have resulted in a semiconductor device comprising or wherein:
referring to claim 17, the chip would have a laminated structure including a substrate (11) and an epitaxial layer (12, as taught by Hiyoshi, para [76]), and would have included the main surface that is formed by the epitaxial layer (12);
referring to claim 18, the epitaxial layer (12, as taught by Hiyoshi) would have been thicker than the substrate (11) (to accommodate elements that constitute the semiconductor device);
and
referring to claim 19, the chip would have a single layered structure (12, as taught by Hiyoshi) consisting of an epitaxial layer (12).
5. Claim 15 is rejected under 35 U.S.C. §103 as being unpatentable over Chew U.S. Patent Application Publication 2022/0102254 A1 (the ‘254 reference) in view of Ohsawa et al. U.S. Patent Application Publication 20210288006.
Referring to claim 15, the ‘254 reference discloses the insulating film (105) as detailed above for claim 13, but does not disclose that the insulating film includes one or both of an inorganic insulating film and an organic insulating film.
Ohsawa, in disclosing a semiconductor device comprising an insulating film (26/27a, Fig. 6), discloses that the insulating film (26/27a) includes one or both of an inorganic insulating film (26, para [28]) and an organic insulating film (polyimide 27a, para [35]), thereby teaching that one or both of an inorganic insulating film and an organic insulating film is a material suitable for an insulating film.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s insulating (105) utilizing one or both of an inorganic insulating film and an organic insulating film. One would have been motivated to make such a modification in view of the teachings in Ohsawa that one or both of an inorganic insulating film and an organic insulating film is a material suitable for an insulating film.
Allowable Subject Matter
6. Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a semiconductor device with all exclusive limitations as recited in claims 6 and 7, which may be characterized (claim 6) in that the pillar electrodes are thicker than the chip, and the sealing insulator is thicker than the chip, and (claim 7) the pillar electrodes have a total planar area amounting to an occupancy ratio of not more than 30% with respect to the planar area of the main surface, and the terminal film has a total planar area amounting to an occupancy ratio of not less than 50% with respect to the planar area of the main surface.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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08-10-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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