Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 2 May 2024.
ALLOWABLE SUBJECT MATTER
Claim 3-12, and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2,13-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated You (US Pat No. 8347042).
As per claim 1, an operation method for a memory device (See FIG 3), the operation method comprising:
starting a first operation cycle in the memory device after the memory device receiving a first operation command (see FIG 4: CMD1 and COL 5 LINES 50-60), the first operation cycle including
a voltage set period (see COL 6 LINES 25-30: “The high voltage generator 130 outputs bias voltages VD, VS, and VW1~VWK in response to the program command PGM.”),
a first operation set period (see FIG 4: T1 and COL 6 LINES 25-30: “The X-decoder 140 selects one of the memory cell blocks MB1˜MBn included in each of the planes PL1˜PLM, on basis of the row address signal RADD.),
a first operation executing period (see FIG 4: T2 and COL 6 LINES 35-45: The page buffers PB1˜PBM select the bitlines of each of the planes PL1˜PLM partially or entirely in response to the column decoding signal CDEC, and then output the latched input data Di1˜DiM to the selected bitlines.”) and
a first operation recovery period (see FIG 4: T3 and COL 6 LINES 10-20 “After storing the input data Di1-DiM in all of the cache buffers CB1-CBM, the logic values of the bits B1-BM are simultaneously changed into logic 0 for the predetermined time T3.”);
switching to a busy status of a cache while starting the voltage set period (see FIG 4: T2 and COL 4 LINES 33-40);
[The ready/busy signal R/Bb is taken as a busy status of a cache.]
receiving data by the cache in the first operation period (see COL 6 LINES 1-10: “The cache buffers CB1-CBM store the input data Di1-DiM one by one in sequence in response to the cache input control signals CIS1-CISM. For instance, the cache buffer CB1 stores the input data Di1 when the cache input control signal CIS1 is enabled.”); and
switching to a ready status from the busy status of the cache while starting the first operation recovery period, such that data in the cache is accessible during the ready status (see FIG 4: T3 and COL 4 LINES 10-20: “Further, the control logic circuit 120 receives the command signal CMD2 in response to the control signals CLE and Web, and disables the ready/busy signal R/Bb for the predetermined time T4 in response to the command signal CMD2.”);
[The disabling of the ready/busy signal in T4 implies the ready/busy signal is enabled prior to that.]
wherein when the second operation command is received by the memory device before the end of the first operation recovery period, the memory device starts a second operation cycle directly after the end of the first operation recovery period, which the second operation cycle includes a second operation set period, a second operation executing period and a second operation recovery period, and the second operation set period is adjacent to the operation recovery period (See COL 4 LINES 34-45: “CMD2”);
[The operation cycle for the second command starts directly after the first operation cycle as per FIG 4.]
wherein the busy status of the cache is switched to the ready status from the busy status while starting the second operation recovery period, such that data in the cache is accessible (See COL 4 LINES 60-65: “CMD3”).
As per claim 2, The operation method of claim 1,
wherein when the second operation command is received after the end of the first operation recovery period, the memory device restarts the first operation cycle after receiving a second operation command and the cache is switched to the busy status (see FIG 4: T3 and COL 4 LINES 10-20: “Further, the control logic circuit 120 receives the command signal CMD2 in response to the control signals CLE and Web, and disables the ready/busy signal R/Bb for the predetermined time T4 in response to the command signal CMD2.”); and wherein the period of the second operation cycle is shorter than the period of the first operation cycle (see COL 1 LINE 65-COL 2 LINE 5).
[The period of the second operation cycle is shorter because the program time according to the invention is reduced.]
As per claim 13, the operation method of claim 2,
wherein the first operation command includes a first write command a data in the cache is written to the memory device during the first operation recovery period; wherein the second operation command includes a second write command and data in the cache is written into the memory device during the second operation recover period (see COL 4 LINES 9-15).
[You discloses the CMD1, CMD2, CMD3 can be read or write commands.]
As per claim 14, You discloses the memory device (see FIG 3: 100), comprising:
a memory cell array configured to store data (see FIG 3: PL1 and COL 3 LINES 60-65);
a control circuit coupled to the memory cell array (see FIG 3: 120), the control circuit including a command interface (see FIG 3: 110) and an operation flow controller (see FIG 3: 130); and
a cache coupled to the memory cell array and the control circuit (see FIG 3: CASH BUFFER (CB1));
wherein after the control circuit receiving a first operation command via the command interface (see FIG 4: CMD1 and COL 5 LINES 50-60), the control circuit control the memory device starting
a first operation cycle including
a first voltage set period (see COL 6 LINES 25-30: “The high voltage generator 130 outputs bias voltages VD, VS, and VW1˜VWK in response to the program command PGM.”),
a first operation set period (see FIG 4: T1 and COL 6 LINES 25-30: “The X-decoder 140 selects one of the memory cell blocks MB1˜MBn included in each of the planes PL1˜PLM, on basis of the row address signal RADD.),
a first operation executing period (see FIG 4: T2 and COL 6 LINES 35-45: The page buffers PB1˜PBM select the bitlines of each of the planes PL1˜PLM partially or entirely in response to the column decoding signal CDEC, and then output the latched input data Di1˜DiM to the selected bitlines.”) and
a first operation recovery period (see FIG 4: T3 and COL 6 LINES 10-20 “After storing the input data Di1-DiM in all of the cache buffers CB1-CBM, the logic values of the bits B1-BM are simultaneously changed into logic 0 for the predetermined time T3.”);
wherein the operation flow controller controls the cache to operate the following procedures:
switching to a busy status of the cache while starting the voltage set period (see FIG 4: T2 and COL 4 LINES 33-40);
[The ready/busy signal R/Bb is taken as a busy status of a cache.]
receiving data by the cache in the first operation period (see COL 6 LINES 1-10: “The cache buffers CB1-CBM store the input data Di1-DiM one by one in sequence in response to the cache input control signals CIS1-CISM. For instance, the cache buffer CB1 stores the input data Di1 when the cache input control signal CIS1 is enabled.”); and
switching to a ready status from the busy status of the cache while starting the first operation recovery period, such that data in the cache is accessible during the ready status (see FIG 4: T3 and COL 4 LINES 10-20: “Further, the control logic circuit 120 receives the command signal CMD2 in response to the control signals CLE and Web, and disables the ready/busy signal R/Bb for the predetermined time T4 in response to the command signal CMD2.”);
[The disabling of the ready/busy signal in T4 implies the ready/busy signal is enabled prior to that.]
wherein when the second operation command is received by the command interface before the end of the first operation recovery period, the control circuit controls the memory device to start a second operation cycle directly after the end of the first operation recovery period, which the second operation cycle includes a second operation set period, a second operation executing period and a second operation recovery period, and the second operation set period is adjacent to the operation recovery period (See COL 4 LINES 34-45: “CMD2”);
[Each operation command proceeds with the same operation cycle.]
wherein the busy status of the cache is switched to the ready status from the busy status by the operation flow controller while starting the second operation recovery period, such that data in the cache is accessible (See COL 4 LINES 60-65: “CMD3”).
As per claim 15, the memory device of claim 14,
wherein the memory device is a NAND memory device further comprises:
a page buffer coupled between the memory cell array and the cache (see FIG 3: PAGE BUFFER (PB1)); and
a data I/O (input/output) circuit coupled to the cache (see FIG 3: 160)
wherein the first operation command includes a first read command (see COL 4 LINES 9-15) .
As per claim 16, the memory device of claim 15,
wherein the first operation cycle further includes a first page buffer to cache period between the first operation executing period and the first operation recovery period (see FIG 4: T3 and COL 4 LINES 10-20: “Further, the control logic circuit 120 receives the command signal CMD2 in response to the control signals CLE and Web, and disables the ready/busy signal R/Bb for the predetermined time T4 in response to the command signal CMD2.”), which the first page buffer to cache period is configured to operate data transferring between the page buffer and the cache (see COL 6 LINES 15-25: “Responding to the cache output control signals COS1-COSM, the cache buffers CB1-CBM output the input data Di1-DiM, that are stored therein, to the page buffers PB1-PBM, respectively, at the same time. As a result, the page buffers PB1-PBM latch the input data Di1-DiM, respectively.”).
As per claim 17, the memory device of claim 16,
wherein the first operation executing period at least includes a first read executing period and a second read executing configured to respectively read data from the memory cell array to the page buffer, and data of the cache outputs to the data I/O circuit during the first operation recovery period (see COL 4 LINES 9-15).
[You discloses the CMD1, CMD2, CMD3 can be read or write commands.]
As per claim 18, the memory device of claim 15,
wherein the second operation command includes a second read command (see COL 4 LINES 9-15);
wherein the second operation cycle further includes a second page buffer to cache period between the second operation executing period and the second operation recovery period, which the second page buffer to cache period is configured to operate data transferring between the page buffer and the cache (see COL 4 LINES 9-15).
[You discloses the CMD1, CMD2, CMD3 can be read or write commands.]
As per claim 19, the memory device of claim 18,
wherein the second operation executing period at least includes a third read executing period and a fourth read executing configured to respectively read data from the memory cell array to the page buffer, and data of the cache outputs to the data I/O circuit during the second operation recovery period (see COL 4 LINES 9-15).
[You discloses the CMD1, CMD2, CMD3 can be read or write commands.]
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 10026473: A non-volatile memory device for selectively performing a recovery operation and a method of operating the same are provided. The method of operating a non-volatile memory device includes receiving a first read command, performing a first sensing operation in response to the first read command, and receiving a second read command. The method further includes completing a memory operation corresponding to the first read command without performing a recovery operation when the second read command is received before the first sensing operation is completed, and performing a second sensing operation in response to the second read command (Abstract).
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137