Prosecution Insights
Last updated: April 19, 2026
Application No. 18/652,901

METHODS AND APPARATUS FOR ARC REDUCTION IN POWER DELIVERY SYSTEMS

Non-Final OA §103
Filed
May 02, 2024
Examiner
KIM, SEOKJIN
Art Unit
2844
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
91%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
418 granted / 540 resolved
+9.4% vs TC avg
Moderate +14% lift
Without
With
+14.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
31 currently pending
Career history
571
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
46.2%
+6.2% vs TC avg
§102
30.0%
-10.0% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 540 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Information Disclosure Statement The information disclosure statement (IDS) submitted on 05/02/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ueki (US 2016/0225559 A1) in view of Nagai (US 2023/0079553 A1). Regarding claim 14, Ueki teaches an apparatus comprising: a baseband management controller (BMC) having a BMC terminal (Fig. 7, USB Controller 13); a comparator (16) having a first comparator input, a second comparator input, and a comparator output, the first comparator input coupled to the configuration terminal (CC, [0085] a CC (Control Channel) terminal); and a deglitch circuit (Signal generation circuit 10, [0041] The signal generation circuit 10 generates the SW control signal for controlling the surge absorber circuit 7) having a deglitch input and a deglitch output ([0041] SW control signals), the deglitch input coupled to the comparator output (output of 16). Ueki does not explicitly teach the BMC terminal of the baseband management controller (BMC) is coupled to the configuration terminal. Nagai teaches an apparatus comprising a baseband management controller (BMC) (Fig. 3, 600, [0070] USB port controller 600) having a BMC terminal coupled to a configuration terminal (Fig. 3, 108, CC). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to recognize that Ueki’s baseband management controller (BMC) has a BMC terminal coupled to the configuration terminal CC as taught by Nagai in order to implement the communication between USB devices as required by USB protocols (Nagai, [0074], [0075]). Regarding claim 15, all the limitations of claim 14 are taught by Ueki in view of Nagai. Ueki further teaches the apparatus, further comprising a controller (Fig. 7, 6, [0041] the control circuit 6) having a controller input, a first controller output, and a second controller output (outputs of circuit 6), the controller input coupled to the deglitch output (output of comparator 16 to 6), wherein the second comparator input is coupled to a reference (Fig. 7, Vref). However, Ueki does not explicitly teach the reference voltage is an output of the controller. Nagai teaches a reference voltage to the comparator is a predetermined threshold voltage ([0073] a threshold voltage, [0077] a predetermined threshold voltage VTH_SRC, which indicates the reference voltage is an output of a processor). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to make the reference voltage input to the comparator of Ueki configurable/programmable by the controller in order to accommodate various voltages to meet USB power delivery standard (Nagai, [0004]). Regarding claim 16, all the limitations of claim 15 are taught by Ueki in view of Nagai. Ueki further teaches the apparatus further comprising a transistor having a first current terminal, a second current terminal, and a control terminal (Fig. 7, M1, M2, M3), the first current terminal coupled to a bus voltage terminal (VBus) and the control terminal coupled to the second controller output (gate terminals are connected to the outputs of 6). Regarding claim 17, all the limitations of claim 16 are taught by Ueki in view of Nagai. Ueki further teaches the apparatus further comprising a variable power supply coupled to the second current terminal (Fig. 7, power supply 5, Abstract a plurality of power supply voltages). Regarding claim 18, all the limitations of claim 16 are taught by Ueki in view of Nagai. Ueki further teaches the apparatus further comprising a load coupled to the second current terminal (Fig. 7, T1, T2, T3). Regarding claim 19, this claim has substantially the same subject matter as that in claim 16. Therefore, claim 19 is rejected under the same rationale as claim 16 above. Allowable Subject Matter Claims 1-13 are allowed. Specifically, the independent claim 1 is allowed over the prior arts. The dependent claims 2-13 are allowed due to their dependencies to the said independent claim 1. The following is an examiner’s statement of reasons for allowance: Regarding claim 1, the prior art Rajasekhar (US 7,391,241 B1) discloses a method comprising setting a deglitch duration to a duration by a counter (Fig. 2). Prior arts do not disclose or fairly suggest, a method comprising: determining, by a controller of a device, whether a length of transmission data is longer than a threshold; responsive to determining that the length of data is longer than the threshold, setting, by the controller a deglitch duration to a duration; and transmitting, by the device, the data, while the deglitch duration has the duration. Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 20, the prior arts fail to teach or reasonably suggest an apparatus, wherein the controller is configured to: responsive to determining that a length of transmission data is longer than a threshold, set a deglitch duration to a duration, and wherein the deglitch circuit is configured to detect a glitch based on the deglitch duration; and transmit data on the configuration channel while the deglitch duration has the duration, in combination with the other limitations of the claim. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H. Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEOKJIN KIM/Primary Examiner, Art Unit 2844
Read full office action

Prosecution Timeline

May 02, 2024
Application Filed
Dec 08, 2025
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
91%
With Interview (+14.0%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 540 resolved cases by this examiner. Grant probability derived from career allow rate.

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