DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Remarks/Arguments
With respect to the rejection of claim 14 under 35 USC 103, Applicant's arguments filed 06/16/2026 have been fully considered but they are not persuasive. Applicant argues, see page 7, paragraph 3:
However, Ueki’s “signal generation circuit 10” does not recite a deglitch circuit. The signal generation circuit 10 in Ueki is described as “generate the SW control signal for controlling the surge absorber circuit 7 based on the power supply control signal”.
Examiner respectfully disagrees. Ueki teaches “The signal generation circuit 10 controls the surge absorber circuit 7 based on the power supply control signal and the ID signal” in paragraph [0073] as Applicant acknowledged above. Since the signal generation circuit 10 controls the surge on the VBUS, it is considered as “a deglitch circuit”.
Applicant further argues, see page 7, paragraph 3:
In particular, the signal generation circuit 10 in Ueki is not described as capable of determining "when the comparator output is logic high for a set duration."
Applicant's arguments above have been fully considered but are moot in view of new grounds of rejection set forth herein as necessitated by Applicant's amendments.
With respect to the rejection of claim 19 under 35 USC 103, Applicant's arguments filed 06/16/2026 have been fully considered but are moot in view of new grounds of rejection set forth herein as necessitated by Applicant's amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Ueki (US 2016/0225559 A1) in view of Nagai (US 2023/0079553 A1).
Regarding claim 14, Ueki teaches an apparatus comprising:
a baseband management controller (BMC) having a BMC terminal (Fig. 7, USB Controller 13);
a comparator (16) having a first comparator input, a second comparator input, and a comparator output, the first comparator input coupled to the configuration terminal (CC, [0085] a CC (Control Channel) terminal); and
a deglitch circuit (Signal generation circuit 10, [0041] The signal generation circuit 10 generates the SW control signal for controlling the surge absorber circuit 7, [0073]) having a deglitch input and a deglitch output ([0041] SW control signals), the deglitch input coupled to the comparator output (output of 16), wherein the deglitch circuit is capable of determining when the comparator output is logic high for a set duration (Fig. 7, [0086] when apparatus 1 and 2 are not connected, CC of apparatus 1 becomes high and CC of apparatus 2 becomes low. The output of comparator 16 is fed to 10. Based on the input from 16 and other inputs from the controller 9, the signal generation circuit 10 outputs control outputs to 7. Therefore, 10 is capable of determining whether the output of 16 is high or low for a duration when the apparatus 1 and 2 are connected to or disconnected from each other).
Ueki does not explicitly teach the BMC terminal of the baseband management controller (BMC) is coupled to the configuration terminal.
Nagai teaches an apparatus comprising a baseband management controller (BMC) (Fig. 3, 600, [0070] USB port controller 600) having a BMC terminal coupled to a configuration terminal (Fig. 3, 108, CC).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to recognize that Ueki’s baseband management controller (BMC) has a BMC terminal coupled to the configuration terminal CC as taught by Nagai in order to implement the communication between USB devices as required by USB protocols (Nagai, [0074], [0075]).
Regarding claim 15, all the limitations of claim 14 are taught by Ueki in view of Nagai.
Ueki further teaches the apparatus, further comprising a controller (Fig. 7, 9, [0041] The control circuit 6 includes a USB power delivery controller 9 having a controller input (Fig. 7, input from VBUS via M4 and C1, [0031] connection cable 3), a first controller output, and a second controller output (outputs of circuit 9), the controller input coupled to the deglitch output (Fig. 7, input from VBUS via M4 and C1), wherein the second comparator input is coupled to a reference (Fig. 7, Vref).
However, Ueki does not explicitly teach the reference voltage is an output of the controller.
Nagai teaches a reference voltage to the comparator is a predetermined threshold voltage ([0073] a threshold voltage, [0077] a predetermined threshold voltage VTH_SRC, which indicates the reference voltage is an output of a processor).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to make the reference voltage input to the comparator of Ueki configurable/programmable by the controller in order to accommodate various voltages to meet USB power delivery standard (Nagai, [0004]).
Regarding claim 16, all the limitations of claim 15 are taught by Ueki in view of Nagai.
Ueki further teaches the apparatus further comprising a transistor having a first current terminal, a second current terminal, and a control terminal (Fig. 7, M1, M2, M3), the first current terminal coupled to a bus voltage terminal (VBus) and the control terminal coupled to the second controller output (gate terminals are connected to the outputs of 9 via 10).
Regarding claim 17, all the limitations of claim 16 are taught by Ueki in view of Nagai.
Ueki further teaches the apparatus further comprising a variable power supply coupled to the second current terminal (Fig. 7, power supply 5, Abstract a plurality of power supply voltages).
Regarding claim 18, all the limitations of claim 16 are taught by Ueki in view of Nagai.
Ueki further teaches the apparatus further comprising a load coupled to the second current terminal (Fig. 7, T1, T2, T3).
Regarding claim 19, this claim has substantially the same subject matter as that in claim 16. Therefore, claim 19 is rejected under the same rationale as claim 16 above.
Regarding claim 21, all the limitations of claim 14 are taught by Ueki in view of Nagai.
Ueki further teaches the apparatus, wherein the set duration indicates a connection to the apparatus has been physically disconnected (Fig. 7, [0086] when apparatus 1 and 2 are not connected, CC of apparatus 1 becomes high and CC of apparatus 2 becomes low. The output of comparator 16 is fed to 10. Based on the input from 16 and other inputs from the controller 9, the signal generation circuit 10 outputs control outputs to 7. Therefore, 10 is capable of determining whether the output of 16 is high or low for a duration when the apparatus 1 and 2 are connected to or disconnected from each other).
Allowable Subject Matter
Claims 1-13 are allowed. Specifically, the independent claim 1 is allowed over the prior arts. The dependent claims 2-13 are allowed due to their dependencies to the said independent claim 1.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, the prior art Rajasekhar (US 7,391,241 B1) discloses a method comprising setting a deglitch duration to a duration by a counter (Fig. 2).
Prior arts do not disclose or fairly suggest, a method comprising: determining, by a controller of a device, whether a length of transmission data is longer than a threshold; responsive to determining that the length of data is longer than the threshold, setting, by the controller a deglitch duration to a duration; and transmitting, by the device, the data, while the deglitch duration has the duration.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 20, the prior arts fail to teach or reasonably suggest a system, wherein the controller is capable of: responsive to determining that a length of transmission data is longer than a threshold, setting a deglitch duration to a duration, and wherein the deglitch circuit is capable of detecting a glitch based on the deglitch duration; and transmitting data on the configuration channel, in combination with the other limitations of the claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at (571) 272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEOKJIN KIM/Primary Examiner, Art Unit 2845
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