CTNF 18/652,934 CTNF 90412 DETAILED ACTION Claims 1 – 13 are pending in the present application. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims recite an arithmetic apparatus which preforms processing based on voltages which are signals and simply describes a relationship between voltage signals and some form of detection result or results which do not have a recited practical application. Specifically, regarding Step 2A. prong 1 (see MPEP 2106.04 II. A. 1. ) the claims recite the limitations “perform arithmetic processing based on a first voltage” and “perform arithmetic processing based on a second voltage”. Next, regarding Step 2A, prong 2 (see MPEP 2106.04 II. A. 2. ) the judicial exception is not integrated into a practical application because the generic processing elements (first / second processing units) do not add significantly more as they amount to simply implementing the abstract idea on or in a generic computer and the operation modes have no structure and are not considered a practical application, just a general link to a field of use. Further, the temperature detection unit is generically recited and considered route data gathering as it either provides for calculation or outputs “a detection result” which is/are (see 112(b) section below) unlinked to the processing units or any practical application. The claims 2-8 do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the selector (claim 2); percentage of analog circuit (claim 5); operation input unit (claim 7); and/or notification unit (claim 8) when considered separately or in combination only amount to generic computer elements moving signals with no resultant practical application which is simply computing at a high level of generality (see MPEP § 2106.05(d) II. ). Regarding Step 2B (see MPEP 2106.04 II. ), for the same the same reasons as step 2a, prong 2, the elements considered alone and together do not amount to something more than the abstract arithmetic processing. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Initially, claim 1 recites the limitation "a detection result" three times in lines 2, 11 and 12. There are antecedent basis issues these limitations in the claim. Further, it is unclear if these recitations of “a detection result” are the same result or different results. It appears that these detection results are distinct as follows: In the first recital “ calculates a detection result obtained by the temperature detection unit” (claim 1, line 2) whereas in the second and third recitals “the temperature detection unit outputs a detection result to the first processing unit in the first mode and outputs a detection result to the second processing unit in the second mode.” (claim 1, lines 12-13). Further, it is unclear what structure implements and is the scope of the limitations that performs the recited functions, as the recitation only states regarding result(s) obtained without the structure to provide the result(s), and a person of ordinary skill in the art would not know the metes and bounds of the structure to provide the result. As best understood, for purpose of examination and in order to expedite prosecution the first recital of a detection result will be considered as a calculated result; and the second and third recitals of a detection result will be considered signal outputs from the temperature detection unit. However, positive in claim recitation of both the metes and bounds applicant intends to claim as well as properly recited antecedent basis is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2, 4, 6-8 and 13 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Murata et al. (JP 2014002081; all reference to attached English Machine Translation; see also IDS of 05/02/2024; hereinafter Murata) . Regarding claim 1 , ( as best understood; see 112(b) section above ) Murata teaches an arithmetic apparatus that comprises a temperature detection unit ( temperature sensitive elements T1# and T2#; see fig. 2 – reproduced below for convivence ) and calculates a detection result ( calculated error in Vf1 and/or Vf2 – see abstract ) obtained by the temperature detection unit ( see at least abstract ), the apparatus comprising: a first processing unit ( 50 ) configured to perform arithmetic processing based on a first voltage ( Vf2; abstract; see fig. 2; see [0038] ); and a second processing unit ( 14 ) configured to perform arithmetic processing based on a second voltage ( Vf1; as output by differential amplifier 26; abstract; see also [0051]; [0039]; and fig. 2 ), wherein the apparatus includes, as operation modes, a first mode of supplying both the first voltage and the second voltage ( when the switch is opposite the configuration shown in fig. 2 see below; then both Vf1 and Vf2 are supplied through amplifier circuit 26 ) and a second mode of suppressing supply of the first voltage ( when the switch is as shown in fig. 2 the output of Vf2 is suppressed and only the output of Vf1 is supplied through the switch to processor 14 ), and the temperature detection unit outputs a detection result to the first processing unit in the first mode ( see fig. 2 showing this output in the first mode ) and outputs a detection result to the second processing unit in the second mode ( see fig. 2 showing this configuration where the output of T1 – i.e. Vf1 is output to processing unit 14 via switch 30 ). Please note: while the citations above are to the specific portions of the prior art that as best understood Examiner felt were most pertinent the document is large and the entire disclosure of the Murata reference is cited broadly for all it teaches (see MPEP 2123 stating that references “are part of the literature of the art, relevant for all they contain.”) PNG media_image1.png 465 827 media_image1.png Greyscale Fig. 2 of Murata Regarding claim 2 , Murata teaches that the temperature detection unit includes a selector configured to switch an output destination of a detection result ( 30; see fig. 2 ). Regarding claim 4 , Murata teaches that in the second mode, supply of the first voltage is stopped, and the second voltage is supplied ( when the switch is as shown in fig. 2 -the second mode- the output of Vf2 to processor 14 is stopped and only the output of Vf1 is supplied through the switch to processor 14 ). Regarding claim 6 , Murata teaches that the first processing unit and the second processing unit are configured to mutually communicate, and one of the first processing unit and the second processing unit corrects a detection result received from the selector based on a detection result received by the other of the first processing unit and the second processing unit ( [0007-08] teaches this configuration for mutual communication and correction of detection results by the first and second calculation means ). Regarding claim 7 , Murata teaches an operation input unit configured to receive an operation input for switching the first mode and the second mode ( at least local shutdown portion of processor 50; [0038] ), wherein the first processing unit and the second processing unit are configured to mutually communicate ( see fig. 2 showing this connectivity and communication via at least switching element 30; see [0043] ), and if the operation input unit receives an operation input for a shift from the first mode to the second mode, the selector outputs a detection result to the second processing unit before the shift ( [0038]; [0043] ), and the first processing unit suppresses the shift if an error between a detection result received by the first processing unit from the selector and a detection result received by the second processing unit from the selector is not less than a reference ( see at least abstract teaching regarding the error calculation and communication of this value transferred as a converted time ratio signal to the control device 14 and regarding the threshold value communicated to the power saving process; see also [0007-08] ). Regarding claim 8 , Murata teaches a notification unit ( at least interface 18 ) configured to output a predetermined notification if the error is not less than the reference ( [0083] ). Regarding claim 13 , Murata teaches electronic equipment comprising: an arithmetic apparatus defined in claim 1 ( see treatment of claim 1 above ); and a driving device ( 20 – drive IC ) configured to perform drive control ( from drive control unit 50; which is part of drive IC 20; see fig. 2; see [0038] ) based on a calculation result concerning a detection result obtained by the temperature detection unit ( abstract; [0038] ) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 3, 5, and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Murata et al. (JP 2014002081; all reference to attached English Machine Translation; see also IDS of 05/02/2024; hereinafter Murata) . Regarding claim 3 , Murata lacks direct and specific teaching that the second voltage is lower than the first voltage. However, Murata does disclose that the voltages are differentially amplified ( via at least differential amplifier 26; see at least [0027] ). Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the differential amplification of the voltage signals of Murata with one of the voltages, here the second voltage, being lower than the other. This is because one of ordinary skill in the art would have expected differing voltages to be one of several straightforward ways of (same or different) to produce the error result providing a differential is the design goal. Regarding claim 5 , Murata lacks direct and specific teaching that the first processing unit is higher in percentage of analog circuit configuration than the second processing unit. However, Murata does disclose that the second processor has a low percentage analog circuit configuration is it is a microcomputer ( [0020] teaches that the second processing unit 14 “is mainly composed of a microcomputer” ). Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the processing unit with a specifically low percentage of analog circuits of Murata with a ratio where the first processing unit has a higher in percentage of analog circuit configuration than the low percentage analog configuration of the second. This is because one of ordinary skill in the art would have expected using analog circuits in the switching control of the first processing unit to be one of several straightforward ways of providing the switching functionality because switching with analog circuitry allows for providing a robust switching control mechanism. Regarding claim 9 , Murata teaches that the temperature detection unit further includes a first resistive element configured to receive the first voltage ( at least resistor between T1 and element 26 receives Vf1; see fig. 2 ), a second resistive element configured to receive the second voltage ( at least resistor between T2 and element 26 receives Vf2; see fig. 2 ). Murata lacks direct and specific teaching regarding an electric element connected in series with both the first resistive element and the second resistive element. However, Murata does disclose that the differential amplifier ( 26 ) is in series with both of the resistors ( see fig. 2 ). Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the differential amplifier in series with the resistors of Murata with a differential amplifier of known configuration having an electric element (such as a resistor) also in series with these resistors (such as a long-tailed pair type differential amplifier which has a series resistor). This is because one of ordinary skill in the art would have expected using a long-tailed pair type differential amplifier as the differential amplifier to be one of several straightforward ways (resistive differential amplifier or semiconductor differential amplifier) of amplification functionality because the differential amplification of the voltage signals is the desired result ( see fig. 2 ). Regarding claim 10 , Murata lacks direct and specific teaching that the electric element is a third resistive element. However, Murata does disclose that the differential amplifier ( 26 ) is in series with both of the resistors ( see fig. 2 ). Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the differential amplifier in series with the resistors of Murata with a differential amplifier of known configuration having an electric element (such as a resistor) also in series with these resistors (such as a long-tailed pair type differential amplifier which has a series resistor). This is because one of ordinary skill in the art would have expected using a long-tailed pair type differential amplifier as the differential amplifier to be one of several straightforward ways (resistive differential amplifier or semiconductor differential amplifier) of amplification functionality because the differential amplification of the voltage signals is the desired result ( see fig. 2 ). Regarding claim 11 , Murata lacks direct and specific teaching that the electric element is a rectifier element. However, Murata does disclose an interface between a high voltage and a low voltage system ( 18; see fig. 2; see [0076] ). Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the voltage interface with any of a variety of known electric elements known to fit a desired design goal such as power/voltage and signal conversion to be used in the device. This is because one of ordinary skill in the art would have expected using a rectifier element for its intended purpose would be conventional and routine in the art of handling voltage signals. This is important in order to provide desired signal types to the processing units to operate on ( see [0076] teaching regarding information/signal conversion to useable forms ). Regarding claim 12 , Murata lacks direct and specific teaching that the selector is arranged in an electric path between each of the first resistive element and the second resistive element and the electric element. However, Murata does disclose that the selector is arranged in series with but after all the elements ( see fig. 2 ). Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the arrangement of the elements such that the selector is between the resistive elements since it has been held that rearranging parts of an invention involves only routine skill in the art (see MPEP 2144.04 (VI-C)). This is important in order to adapt the device to a design indicated layout while retaining the state function of directing the temperature signals to different processors as desired. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHILIP COTEY whose telephone number is (571)270-1029. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Laura Martin can be reached at 571-272-2160. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHILIP L COTEY/ Examiner, Art Unit 2855 /LAURA MARTIN SWEENEY/ Supervisory Patent Examiner, Art Unit 2855 Application/Control Number: 18/652,934 Page 2 Art Unit: 2855 Application/Control Number: 18/652,934 Page 3 Art Unit: 2855 Application/Control Number: 18/652,934 Page 4 Art Unit: 2855 Application/Control Number: 18/652,934 Page 5 Art Unit: 2855 Application/Control Number: 18/652,934 Page 6 Art Unit: 2855 Application/Control Number: 18/652,934 Page 7 Art Unit: 2855 Application/Control Number: 18/652,934 Page 8 Art Unit: 2855 Application/Control Number: 18/652,934 Page 9 Art Unit: 2855
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