Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/09/2024, 2/09/2025, and 4/29/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
Claim 8 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation " the first control algorithm comprises a proportional plus integral control algorithm” in line 1. Examiner recommends applicant changes “The” to “A” There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-4, 9, 12-13, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Torrico-Bascope (U.S. Publication No 2022/0103094) in view of Pahlevaninezhad et. al. (U.S. Publication No 2015/0236617 A1).
Regarding claim 1 and 12, Torrico-Bascope et. al. teaches an apparatus (e.g. Fig. 1) comprising:
a bi-directional AC/DC power conversion topology (e.g. 100)(Fig. 1) comprising: a low frequency switching network (e.g. 60)(Fig. 1), a high frequency switching network (e.g. 50)(Fig. 1), and one or more inductors (e.g. 130, 140)(Fig. 1), wherein the high frequency switching network comprises a plurality of high frequency switching devices (e.g. 152, 153, 154, 155)(Fig. 2), and the power conversion topology is configured to transfer power between a DC voltage (e.g. 170)(Fig. 1) and an AC voltage (e.g. 110)(Fig. 1); Torrico-Bascope et. al. does not teach a controller coupled to the power conversion topology, and wherein the controller is configured to: receive the DC voltage, the AC voltage, and a total current flowing through the one or more inductors; generate a duty cycle based on a reference signal and a controlled signal; determine a switching frequency based on the total current, the duty cycle, and one or more of the DC voltage and the AC voltage; and generate the high frequency switch control signals based on the switching frequency and the duty cycle. wherein the high frequency switch control signals are configured to operate the high frequency switching devices.
However, Pahlevaninezhad et. al. discloses a controller (e.g. 70 and 60)(Fig. 5) coupled to the power conversion topology, and wherein the controller is configured to: receive the DC voltage (e.g. Vdc)(Fig. 5), the AC voltage (e.g. Vg)(Fig. 5), and a total current (e.g. ig)(Fig. 5) flowing through the one or more inductors (e.g. Lg)(Fig. 4); generate a duty cycle (e.g. D)(Fig. 5) based on a reference signal (e.g. igref)(Fig. 5) and a controlled signal (e.g. Vg)(Fig. 5); determine a switching frequency (e.g. fswopt)(Fig. 5) based on the total current (e.g. ig)(Fig. 5), the duty cycle (e.g. D)(Fig. 5), and one or more of the DC voltage (e.g. Vdc)(Fig. 5) and the AC voltage (e.g. Vg)(Fig. 5); and generate the high frequency switch control signals (e.g. output of 80)(Fig. 5) based on the switching frequency (e.g. fswopt)(Fig. 5) and the duty cycle (e.g. D)(Fig. 5). wherein the high frequency switch control signals are configured to operate the high frequency switching devices (e.g. S1, S2)(Fig. 1). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a controller coupled to the power conversion topology, and wherein the controller is configured to: receive the DC voltage, the AC voltage, and a total current flowing through the one or more inductors; generate a duty cycle based on a reference signal and a controlled signal; determine a switching frequency based on the total current, the duty cycle, and one or more of the DC voltage and the AC voltage; and generate the high frequency switch control signals based on the switching frequency and the duty cycle. wherein the high frequency switch control signals are configured to operate the high frequency switching devices in Torrico-Bascope et. al. as taught by Pahlevaninezhad et. al, because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Regarding claim 2 and 16, Torrico-Bascope et. al. teaches wherein, when operating as a rectifier, determining the switching frequency is based on the DC voltage (Para [0009], “In an embodiment, the first high frequency switching cell includes a first high frequency switching device connected between a first DC voltage and the midpoint of the first high frequency switching cell, and a second high frequency switching device connected between the midpoint of the first high frequency switching cell and a second DC voltage. The totem-pole switch arrangement allows pulse-width modulation (PWM) control of the output power”).
Torrico-Bascope et. al. does not teach when the apparatus operating as an inverter, determining the switching frequency is based on the DC voltage and the AC voltage.
However, Pahlevaninezhad et. al. discloses when the apparatus operating as an inverter, determining the switching frequency is based on the DC voltage and the AC voltage (Para [0065], “…The optimal switching frequency f.sub.sw is output from the optimal frequency calculator 60 to the PWM Modulator 80. The optimal frequency calculator 60 receives, as input, the value d from the current controller 70, the inverter voltage input V.sub.dc and the current output i.sub.g from the voltage-source inverter 87, and the grid voltage v.sub.g”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have when the apparatus operating as an inverter, determining the switching frequency is based on the DC voltage and the AC voltage in Torrico-Bascope et. al. as taught by Pahlevaninezhad et. al, because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Regarding claim 3, 13, and 17, Pahlevaninezhad et. al teaches wherein the switching frequency is configured to create an available charge provided by an inductor during a dead time equal to a stored charge in an output capacitance of the high frequency switching devices (Para [0055], “L.sub.M is a mutual inductance of the auxiliary inductor and the output inductor, [0057] L.sub.g is a self inductance of the output inductor, [0058] L.sub.aux is a self inductance of the auxiliary inductor, [0059] C.sub.so is an equivalent output capacitance of the power semiconductors, [0060] V.sub.dc is an input voltage of the inverter, [0061] V.sub.g is the grid voltage, [0062] t.sub.d is a dead time between pulses of the power semiconductors, and [0063] d is the duty ratio”).
Regarding claim 4 and 18, Pahlevaninezhad et. al teaches wherein the switching frequency is limited to a predetermined maximum frequency. (Para [0065], “FIG. 5 shows the block diagram of the closed-loop control system for the ZVS voltage source inverter according to another aspect of the invention. In FIG. 5, the closed-loop control system includes a control loop which adjusts the duty ratio d and a control loop which determines the optimal switching frequency f.sub.sw”).
Regarding claim 9, Pahlevaninezhad et. al teaches wherein, when operating as an inverter, the reference signal comprises an AC reference current (e.g. Igref)(Fig. 6), the controlled signal comprises an AC current corresponding to the AC voltage (e.g. ig)(Fig. 6), and the controller is configured to: determine a first error signal (e.g. output of 650)(Fig. 6) by subtracting the AC current from the AC reference current and generate the duty cycle (e.g. D)(Fig. 6) by applying a first control algorithm (e.g. 660)(Fig. 6) to the first error signal.
6. Claims 5-6 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Torrico-Bascope (U.S. Publication No 2022/0103094) and Pahlevaninezhad et. al. (U.S. Publication No 2015/0236617 A1) in further view of Gu et. al. (U.S. Publication No 2021/0226528).
Regarding claim 5 and 19, Torrico-Bascope and Pahlevaninezhad et. al. teaches the subject matter in claims 1 and 12, a bi-directional AC/DC power conversion topology.
Torrico-Bascope and Pahlevaninezhad et. al. fail to disclose wherein the power conversion topology comprises one or more phases.
However, Gu et. al. discloses wherein the power conversion topology comprises one or more phases (Fig. 1).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have wherein the power conversion topology comprises one or more phases in Torrico-Bascope et. al. and Pahlevaninezhad et. al. as taught by Gu et. al., because it provides for a lower load currents using multiple phases, thus increasing operational efficiencies.
Regarding claims 6 and 20, Gu et. al. discloses wherein the controller is configured to; determine an average current by applying a low pass filter to the total current; and determine the switching frequency based on the average current (Para [0044], “FIG. 2, the converter 200 may include a single current sensing circuit. The single current sensing circuit senses current that passes through the resistors 236 and 238, which represents the sum of currents for all phases of the converter 200”)(Para [0045], “If the sensed current is less than a boundary condition, the sensed current may indicate that the converter 200 is operating in a discontinuous mode. For example, if the sensed current is less than the boundary condition, the current through one of the phases (e.g., through the inductor 228 or 230), may be discontinuous”).
7. Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Torrico-Bascope (U.S. Publication No 2022/0103094) and Pahlevaninezhad et. al. (U.S. Publication No 2015/0236617 A1) in further view of Afridi et. al. (U.S. Publication No 2021/0194356).
Regarding claims 7 and 14, Torrico-Bascope and Pahlevaninezhad et. al. teaches the subject matter in claims 1 and 12, a controller coupled to the power conversion topology.
Torrico-Bascope and Pahlevaninezhad et. does not teach wherein, when operating as an inverter, the reference signal comprises an AC reference voltage, the controlled signal comprises the AC voltage, and the controller is configured to: determine a first error signal by subtracting the AC voltage from the AC reference voltage; and generate the duty cycle by applying a first control algorithm to the first error signal. However, Afridi et. al. discloses wherein, when operating as an inverter, the reference signal comprises an AC reference voltage (e.g. Vout.ref)(Fig. 6), the controlled signal comprises the AC voltage (e.g. Vout.sensed)(Fig. 6), and the controller (e.g. inverter side dual mode controller)(Fig. 6) is configured to: determine a first error signal (e.g. Ez)(Fig. 6) by subtracting the AC voltage from the AC reference voltage (Fig. 6); and generate the duty cycle (e.g. Dbuck/Dbuckboost)(Fig. 6) by applying a first control algorithm (e.g. 170/172)(Fig. 6) to the first error signal.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have wherein, when operating as an inverter, the reference signal comprises an AC reference voltage, the controlled signal comprises the AC voltage, and the controller is configured to: determine a first error signal by subtracting the AC voltage from the AC reference voltage; and generate the duty cycle by applying a first control algorithm to the first error signal in Torrico-Bascope et. al. and Pahlevaninezhad et. al. as taught by Afridi et. al., because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
8. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Torrico-Bascope (U.S. Publication No 2022/0103094) and Pahlevaninezhad et. al. (U.S. Publication No 2015/0236617 A1) in further view of Choudhury (U.S. Patent No 9966841).
Regarding claim 10, Torrico-Bascope and Pahlevaninezhad et. al. teaches the subject matter in claims 1, generate a duty cycle based on a reference signal.
Torrico-Bascope and Pahlevaninezhad et. al. does not disclose wherein, when operating as an inverter, the reference signal comprises an AC reference voltage, the controlled signal comprises the AC voltage, and the controller is configured to: determine a first error signal by subtracting the AC voltage from the AC reference voltage; generate a second reference signal by applying a voltage loop control algorithm to the first error signal; determine a second error signal by subtracting the AC current from the first error signal and generate the duty cycle by applying a current loop control algorithm to the second error signal.
However, Choudhury discloses wherein, when operating as an inverter, the reference signal comprises an AC reference voltage (e.g. Vref)(Fig. 1B), the controlled signal comprises the AC voltage (e.g. Vb)(Fig. 1B), and the controller is configured to: determine a first error signal (e.g. output of 110)(Fig. 1B) by subtracting the AC voltage from the AC reference voltage; generate a second reference signal by applying a voltage loop control algorithm (e.g. 112)(Fig. 1B) to the first error signal; determine a second error signal (e.g. output of 120)(Fig. 1B) by subtracting the AC current (e.g. isen)(Fig. 1B) from the first error signal (e.g. iref)(Fig. 1B) and generate the duty cycle (e.g. output of 122)(Fig. 1B) by applying a current loop control algorithm (e.g. 122)(Fig. 1B) to the second error signal. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have wherein, when operating as an inverter, the reference signal comprises an AC reference voltage, the controlled signal comprises the AC voltage, and the controller is configured to: determine a first error signal by subtracting the AC voltage from the AC reference voltage; generate a second reference signal by applying a voltage loop control algorithm to the first error signal; determine a second error signal by subtracting the AC current from the first error signal and generate the duty cycle by applying a current loop control algorithm to the second error signal in Torrico-Bascope et. al. and Pahlevaninezhad et. al. as taught by Choudhury, because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Allowable Subject Matter
9. Claims 11 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 11 and 15, none of the prior art, made of record, singularly or in combination, teaches or fairly suggest wherein, when operating as a rectifier, the reference signal comprises a DC reference voltage, the controlled signal comprises the DC voltage, and the controller is configured to: determine a DC voltage error signal by subtracting the DC voltage from the DC reference voltage; generate a voltage control signal by applying a DC voltage loop control algorithm to the voltage error signal;generate an AC current reference signal by multiplying the voltage control signal by an absolute value of the AC voltage; determine an AC current error signal by subtracting an absolute value of the AC current from the AC current reference signal; and generate the duty cycle by applying an AC current loop control algorithm to the AC current error signal.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN W SOILEAU whose telephone number is (571)272-6650. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CT.
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/JONATHAN WALTER SOILEAU/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838