Prosecution Insights
Last updated: October 02, 2026
Application No. 18/653,082

RECTIFIER WITH SIGNAL RECONSTRUCTION

Non-Final OA §103§112
Filed
May 02, 2024
Priority
Jun 30, 2021 — continuation of 11/984,802
Examiner
DUDA, RINA I
Art Unit
2846
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
3 (Non-Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
817 granted / 1019 resolved
+12.2% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
26 currently pending
Career history
1040
Total Applications
across all art units

Statute-Specific Performance

§101
4.2%
-35.8% vs TC avg
§103
37.9%
-2.1% vs TC avg
§102
33.0%
-7.0% vs TC avg
§112
18.4%
-21.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1019 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/22/26 has been entered. Allowable Subject Matter The indicated allowability of claims 1-17 is withdrawn in view of the newly discovered reference(s) to Nakano. Rejections based on the newly cited reference(s) follow. Additionally, the claims will also be rejected under 35 USC 112 (a) and (b) since the scope of the recited invention is not reasonably certain and the original specification does not support the use of the recited combination of electrical components in “any” type of “apparatus”. Response to Arguments Applicant's arguments filed 7/22/26 have been fully considered but they are not persuasive. Contrary to applicant’s assessment of the new amendment to claims 18-20, the new language does not overcome the 35 USC 112b rejection presented in the last Office Action. The non-obvious type double patenting rejection of the pending claims is overcome by the terminal disclaimer filed and approved on 6/24/26. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The original specification does not have support for using a combination of generic electrical components such as rectifiers, drivers, sensors, resistors, isolation barriers including capacitors, operational amplifiers, and comparators in any type of “apparatus”. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Each claim must have three parts: a preamble, a transitional phrase, and a body. The preamble is supposed to define the invention with definite and clear terms so that one skilled in the art can determine the scope of the invention. The combination of the current preamble/transitional phrase/body fails to provide a complete definition of the “apparatus”, since it is not tied to a specific structure, function, or environment. Furthermore, the claims only list a series of components without reciting any functional language. When a claim lists components without explaining how they interact or cooperate with each other to perform a function, the claim will be rejected for being indefinite for lacking utility. The pending claims recite internal details of an “apparatus” but they never explicitly state what “the apparatus” does or its intended technical environment. In order to overcome this rejection, applicant must amend the claims to recite a proper preamble that clearly defines the claimed invention and a body that no only lists the structural elements of a novel system but also recites the functions of said elements. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 5-7, 16-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakano (US Patent 5134307). The pending claims have been rejected under 35 USC 112 (b) for being vague and indefinite. Since the method of forming “the apparatus” is not germane to the issue of patentability of the “apparatus” itself, prior art will be applied to the invention as best understood by the examiner. The claims do not include what the “apparatus” does or in what environment it operates, they only recite a list of electrical components connected to each other without a purpose. Claim 1, Nakano teaches “an apparatus” comprising: a signal generation circuit having first and second outputs (described for example by the outputs connected to power supply 15 that includes transistors Q1-Q4; a rectifier circuit 70 having first and second inputs and first and second outputs; an isolation circuit 44 coupled between the first and second outputs of the signal generation circuit and the first and second inputs of the rectifier circuit 70; a detector 31 coupled to the rectifier circuit (see fig. 1); and a driver circuit including at least inverter 77 which comprises a power terminal 75, a reference terminal 76, a driver input connected to charging circuit 72, storage battery BT, and blocking diode DB, and a driver output connected to terminals T3/T4, wherein the power terminal is coupled to the first rectifier output, the reference terminal is coupled to the second rectifier output, and the driver input that is connected to the charging circuit/storage battery/blocking diode is also connected to the detector output. The claimed language does not specify what kind of connection there is between the driver and the detector. It would have been obvious to one person of ordinary skill in the art at the time the invention was filed to interpret the description of Nakano’s system to mean that the output of the detector circuit is electrically (indirectly) connected to the input of the driver, since the output of the detector 31 is inputted into an error amplifier 38 which determines a difference between the detected voltage and a reference voltage and said difference is used to regulate the voltage outputted by inverter 77 in order to reduce electromagnetic interference problems (as described in col. 1 lines 66-68 and col. 2 lines 1-2). Claims 5-6, Nakano teaches a rectifier circuit 70 having a first, second, third, and fourth rectifying diodes D5-D8. Claim 7, it is well known to have rectifiers comprising a plurality of transistors. Claim 16, Nakano teaches isolation circuit 44 including capacitors C1/C2 connected to the first and the second inputs of rectifier circuit 70. Claim 17, Nakano discloses the claimed invention except for the recited electrical components being part of an integrated circuit. It would have been obvious to one person of ordinary skill in the at the time the invention was filed to include the electrical components into one integrated circuit, since it has been held that forming in one piece a system which has formerly been formed in multiple pieces and put together involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893). Claim 18, Nakano teaches an apparatus comprising an electrical circuit (as shown in fig. 1) having first and second inputs connected to terminals C/D of circuit 44 and an output, the electrical circuit comprises a rectifier 70 having first and second inputs coupled to the first and second inputs of the electrical circuit (as shown in fig. 1) and having first and second outputs; and a driver circuit including at least inverter 77 which comprises a power terminal 75, a reference terminal 76, a driver input connected to charging circuit 72, storage battery BT, and blocking diode DB, and a driver output, wherein the power terminal is connected to the first rectifier output, the reference terminal is coupled to the second rectifier output, and the driver input that is connected to the charging circuit/storage battery/blocking diode is also connected to the output of the electrical circuit through a detector 31. The claimed language does not specify what kind of connection there is between the driver and the electrical circuit. It would have been obvious to one person of ordinary skill in the art at the time the invention was filed to interpret the description of Nakano’s system to mean that the output of the detector is electrically (indirectly) connected to the output of the electrical circuit, since the output of the detector 31 is inputted into an error amplifier 38 which determines a difference between a detected voltage and a reference voltage and said difference is used to regulate the voltage outputted by power supply 15 to rectifier 70 and battery BT in order to reduce electromagnetic interference problems (as described in col. 1 lines 66-68 and col. 2 lines 1-2). Claim 20, Nakano teaches, for example in fig. 1, a series of circuits that include a signal generation circuit that may include elements 12/15 and an isolation circuit 44 coupled between outputs of the signal generation circuit and the first and second inputs of the electrical circuit. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional documents listed in the attached PTO-892 describe other systems that include the recited electrical components. Although, claims 3-4, 8-15, and 19 have not been rejected using prior art, they have been rejected under 35 USC 112(a) and (b) and are considered not allowable in their current form. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Rina I Duda whose telephone number is (571)272-2062. The examiner can normally be reached M-F 8-4 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eduardo Colon Santana can be reached at (571) 272-2060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RINA I DUDA/Primary Examiner, Art Unit 2837
Read full office action

Prosecution Timeline

May 02, 2024
Application Filed
Oct 22, 2025
Non-Final Rejection mailed — §103, §112
Jan 22, 2026
Response Filed
Feb 24, 2026
Final Rejection mailed — §103, §112
Jun 24, 2026
Response after Non-Final Action
Jul 22, 2026
Request for Continued Examination
Jul 25, 2026
Response after Non-Final Action
Aug 12, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
90%
With Interview (+10.1%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1019 resolved cases by this examiner. Grant probability derived from career allowance rate.

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