Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election of Species B in the reply filed September 8, 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)). Claims 3-5 and 7-9 drawn to the non-elected species have been withdrawn from examination for patentability.
Drawings
Figures 13 and 17 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6 and 11 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
In claim 6, the feature that the circuit comprises a FET having source and drain terminals connected respectively to the DC voltage and the higher DC voltage is inconsistent with the elected Species B in Fig. 8. For example, in Fig. 8, IC circuits corresponding to the claimed circuit has terminals connected to VDD’ (e.g., the claimed higher DC voltage) and ground, not VDD (e.g., the claimed DC voltage) and VDD’.
For the purpose of prior art rejection(s) below, the feature has been interpreted to require that the claimed circuit is connected to the higher DC voltage.
In claim 11, the feature that the claimed circuit is powered by a higher DC voltage, the higher DC voltage is greater than the DC voltage plus a threshold voltage, and the AC waveforms transition between the DC voltage and the voltage greater than the DC voltage plus a threshold voltage to generate a supply volage for the circuit at the higher DC voltage is inconsistent with the elected Species B in Fig. 8. For example, in Figs. 8-9, 3, while the gate voltages VG1-VG4 (e.g., the claimed higher DC volage) alternate between a higher DC voltage (>VDD+Vth) and the DC voltage VDD, IC circuits in Fig. 8 corresponding to the claimed circuit is powered by VDD’ (e.g., the claimed higher DC voltage), not (>VDD+Vth); VDD’ and >VDD+Vth are different in Figs. 8 and 9.
For the purpose of prior art rejection(s) below, the feature has been interpreted to require that the higher DC voltage is applied at the gates of the claimed n-channel FETs and that the circuit is not powered by the higher DC voltage.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
First 102 rejection
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 4,308,468 to Olson.
With respect to claim 1, Olson discloses in Fig. 2 a multiphase switch connected between a DC voltage (e.g., 1 may be a DC voltage at a point of time as discussed below) and a circuit to be powered by a higher DC voltage (e.g., DC voltage at a point in time as sampled by capacitor 8 is higher than ground), comprising
a plurality of n-channel FETs (e.g., NFETs 2 and 25) disposed in parallel between the DC voltage (e.g., 1) and the circuit (e.g., 8) to be powered by the higher DC voltage,
wherein the n-channel FETs (e.g., 2 and 10) each have a gate, and wherein the gates of the n-channel FETs (e.g., 2 and 10) are driven by AC waveforms (e.g., S for 2 and /S for 10) of different phases. As to the feature of the multiphase switch (e.g., 2 and 10) being connected between a DC voltage and a circuit, such a feature is considered to be a recitation of the intended use of the claimed invention: the claimed invention does not positively recite a DC voltage source producing the DC voltage as an element of the claimed invention. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Here, the multiphase switch (e.g., 2 and 10) in Fig. 2 of Olson is capable of the recited use (e.g., although a variable voltage is applied commonly (e.g., Col. 1 ll. 11-15), voltage source 1 may be any voltage source (e.g., Col. 1 ll. 61-64) including a voltage source producing different DC voltages at different times, and at any such a moment, the DC voltage of 1 is a DC voltage for that moment).
Second 102 rejection
With respect to claim 1, Nobauer discloses in Figs. 1-2 and 10 a multiphase switch connected between a DC voltage (e.g., 62) and a circuit (e.g., 3) to be powered by a higher DC voltage (e.g., DC voltage at 61 is higher than ground at 63 as shown in Fig. 10), comprising
a plurality of n-channel FETs (e.g., 1-2) disposed in parallel between the DC voltage (e.g., 62) and the circuit (e.g., 3) to be powered by the higher DC voltage,
wherein the n-channel FETs (e.g., 1-2) each have a gate, and wherein the gates of the n-channel FETs (e.g., 1-2) are driven by AC waveforms (e.g., DRV1-DRV2 are each a phase and different in phase in that a phase of DRV2 starts with a delay of Td1 compared to DRV1) of different phases. As to the feature of the multiphase switch (e.g., 1-2) being connected between a DC voltage and a circuit, such a feature is considered to be a recitation of the intended use of the claimed invention: the claimed invention does not positively recite a DC voltage source producing the DC voltage as an element of the claimed invention. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Here, the multiphase switch (e.g., 1-2) in Fig. 1 of Nobauer is capable of the recited use (e.g., voltage source 62 may be a voltage source producing different DC voltages at different times, and at any such a moment, the DC voltage of 1 is a DC voltage for that moment).
With respect to claim 6, insofar as understood, the circuit (e.g., 3) comprises a FET having a terminal connected to the higher DC voltage (e.g., 61).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Olson.
With respect to claim 2, Olson fails to disclose that 24 and 26 are each 2 NFETs connected in parallel. However, it was notoriously well-known in the art to a person of skill in the art before the effective filing date of the claimed invention that a transistor conducting a current can be implemented by parallel-connected transistors conducting smaller currents to save costs and/or conduct smaller currents through each MOSFET and thus reduce stress on the transistor; an official notice of the foregoing fact is hereby taken. Thus, it would have been obvious to a person of ordinary skill in the art to implement each of transistors 2 and 10 in Fig. 2 of Olson using the notoriously well-known method of forming a switch with parallel-connected switches because such a modification would reduce costs and/or enable smaller currents to flow through each MOSFET to reduce stress through the switch.
With respect to claim 10, Olson discloses in Fig. 2 a multiphase switch (e.g., 2 and 10) but fails to disclose that MOSFETs 2 and 10 are implemented in GaN technology with GaN FETs, and incorporated in a GaN integrated circuit. However, it was notoriously well-known in the art to a person of skill in the art before the effective filing date of the claimed invention that a GaN HEMT transistor may be used in place of MOSFETs for increased speed/power. Therefore, it would have been obvious to use a GaN HEMT transistor in place of MOSFETs 2 and 10 in Fig. 2 of Olson to obtain an increased speed/power.
With respect to claim 11, insofar as understood, as to the feature that the higher DC voltage is greater than the DC voltage plus a threshold voltage, and the AC waveforms transition between the DC voltage and the voltage greater than the DC voltage plus a threshold voltage to generate a supply voltage for the circuit at the higher DC voltage, such a feature is considered to be a recitation of the intended use of the claimed invention: the claimed invention does not positively recite a DC voltage source producing the DC voltage and AC waveform generator producing the AC waveforms as elements of the claimed invention. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Here, the multiphase switch (e.g., 2 and 10) in Fig. 1 of Olson is capable of the recited use (e.g., receiving a DC voltage at 1 higher than the higher DC voltage at 7 plus a threshold voltage and AC waveforms S and /S transitioning between the DC voltage 1 plus a threshold voltage to generate a supply voltage for 8 at the higher DC voltage at 7).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Lincoln Donovan, can be reached at (571)272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2842