DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/02/2024 is in compliance with the provisions of 35 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Drawings
The drawings are objected to because
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Fig. 3, 302: although it is readable that DDR is the in the box, the font is difficult to read
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Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 5 and 18 objected to because of the following informalities:
Claim 5 recites “each of the first region and the second comprises four CIT regions.” The noun “region” is omitted after “the second.” While the meaning is inferrable from dependent claim 4, this is a typographical error that must be corrected. Applicant is required to amend claim 5 to read “each of the first region and the second region comprises four CIT regions.”
Claim 18 is an apparatus claim (UE) that includes the active method step “storing the coherent correlation results across four CIT regions of a CIT memory.” Using an active method step in a structural apparatus claim creates a drafting inconsistency. The scope is not genuinely ambiguous, and therefore no § 112(b) rejection is raised. However, Applicant is invited to recast the limitation in structural language, e.g., “a CIT memory configured to store coherent correlation results across four CIT regions of the CIT memory, wherein each CIT region comprises 320 correlator taps,”.
Appropriate correction is required.
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0022] reads “FIG. 11 is a diagram illustrating forms of storage for correlation processing at the ISM, according to an embodiment” without a terminal period. All other figure description paragraphs are properly punctuated.
Paragraph [0071] states: “the ucHRC SS2 may requests the next 4 ms of data.” “Requests” should be “request.”
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Paragraph [0087] refers to “A gather module (or frequency selection module) 2112,” but reference numeral 2112 in FIG. 21 corresponds to the code generator, not the gather/frequency selection module. The gather module in FIG. 22 is labeled 2212.
Paragraph [0096] introduces FIG. 25 as a block diagram in “network environment 2300,” but the correct reference numeral as shown in the figure itself is 2500. Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
The terms "first high-resolution correlation (HRC) engine” and “second HRC engine”, in claim 14, are coined terms that do not connote a sufficiently definite structure to one of ordinary skill in the art standing alone. “Engine” is a nonce term similar to “module,” “unit,” or “mechanism,” all of which have been found to invoke § 112(f) treatment. In the independent claims, these terms are defined solely by function: “configured to perform coherent correlation and accumulation” and “configured to process coherent correlation results.”
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1–3, 12-16, and 19-20 are rejected under 35 U.S.C. § 103 as being unpatentable over Lennen (US 2010/0134354 A1) in view of Conflitti et al. (US 2022/0137236 A1).
Regarding Claim 1, Lennen (‘354) in view of Conflitti et al. (‘236) teaches:
Lennen (‘354) teaches: a method comprising: loading data from a memory to an input sample memory (ISM) of a user equipment (UE), wherein the data corresponds to input from an L5 antenna of the UE. Lennen (‘354) teaches an input sample subsystem 302 that receives signal data and stores the digitized input samples in RAM 404 serving as the input sample memory ([0026]: “The input sample subsystem 302 receives signal data from the RF component 202, FIG. 2, and stores the signal data in RAM that is part of the memory subsystem 308.”) ([0030]: “The input signal may be divided into digital samples in the input sample processing subsystem 402 with the output being stored in random access (RAM) memory 404.”).
Lennen (‘354) does not explicitly teach that the data corresponds to input from an L5 antenna specifically, but Conflitti et al. (‘236) teaches a GNSS receiver dedicated to the E5/L5 band, in which baseband sample memory (BSM) element 468 stores sample data sourced from an L5/E5 antenna input ([Abstract]: “GNSS receivers and systems within such receivers use improvements to reduce memory usage while providing sufficient processing resources to receive and acquire and track E5 band GNSS signals directly.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the input sample memory architecture of Lennen (‘354) with the L5-only antenna input of Conflitti et al. (‘236). One would have been motivated to do so because Conflitti et al. (‘236) explicitly teaches that restricting the receiver to the L5/E5 band reduces hardware and memory complexity compared to a dual-band design while still achieving signal acquisition and tracking objectives for that band. A person of ordinary skill in the art would have had a reasonable expectation of success because both references address the same GPS/Galileo L5 signal frequency band.
Lennen (‘354) teaches: performing, by a first high-resolution correlation (HRC) engine of the UE, coherent correlation and accumulation on the data for at least one code-frequency offset combination, to generate coherent correlation results. Lennen (‘354) teaches a signal processing subsystem 304 that includes matched filter 408, coder 410, carrier and code NCO 412, and coherent summation block 418, which together perform coherent correlation of input samples from RAM 404 against a local PN code replica for a given code-frequency offset combination, accumulating the I, Q output in coherent memory 420 — collectively functioning as the first HRC engine ([0033]: “The signal processor subsystem 404 may also include a matched filter 408, coder 410, carrier and code numeric coded oscillator (NCO) 412, cross-correlator block 414, cross-correlation removal block 416, and a coherent summation block 418.”) ([0130]: “The I and Q output of the match filter is stored in the coherent buffer (coherent memory) 420.”).
Lennen (‘354) teaches: processing, by a second HRC engine of the UE, the coherent correlation results by at least performing frequency widening and non-coherent accumulation to generate non-coherent correlation results indicating at least peak accumulations of correlations. Lennen (‘354) teaches FFT block 422 that reads coherent memory 420 and transforms the coherent results into the frequency domain, evaluating multiple Doppler frequency bins simultaneously and widening the frequency search range per hypothesis. Block 424 computes the magnitude of each FFT output bin, and non-coherent memory 432 accumulates those magnitudes across successive coherent integration intervals to generate non-coherent correlation results from which peak accumulations are identified ([0041]: “The FFT subsystem 306 may include a multiplexer 421 that multiplexes the output of the matched filter 408 and data from the coherent buffer 420 and may be coupled to the Fast Fourier Transfer (FFT) block 422. The FFT subsystem 306 may also include a second multiplexer 423, a filter block 424, and a sorter block 426. The output of the FFT subsystem 306 may be from the sorter 426 to a detector block 428, from the non-coherent summation of the signal magnitude 424 to the non-coherent RAM 432.”) ([0131]: “The output of the coherent memory 420 is then processed by the FFT 422. The FFT 422 enables short coherent integrations and combines them. The absolute value or normalization of the output of the FFT 422 occurs in block 424. The normalized value from block 424 may be referred to as non-coherent data and is then stored in the non-coherent memory 432.”).
Regarding Claim 2, Lennen (‘354) in view of Conflitti et al. (‘236) teaches the method of claim 1, and further:
Lennen (‘354) teaches: processing, by a front end processor (FEP) of the UE, the input from the L5 antenna after conversion into a digital data stream. Lennen (‘354) teaches input sample processing subsystem 302 as the front end processor, which divides the received RF signal into digital samples and stores the output in RAM memory 404 for subsequent signal processing ([0030]: “The input signal may be divided into digital samples in the input sample processing subsystem 402 with the output being stored in random access (RAM) memory 404. The RAM may be any type of read/write memory that may be written to and read from at a rate to keep data flowing between the input sample subsystem 302 and the signal processing subsystem 304.”).
Lennen (‘354) does not explicitly teach, but Conflitti et al. (‘236) teaches: saving the processed data at the memory, wherein the memory comprises an external double data rate (DDR) memory. Lennen (‘354)’s RAM 404 is not described as external DDR memory. Conflitti et al. (‘236) teaches a system-on-chip architecture in which the GNSS processing system is coupled via a bus interface to dynamic random access memory (DRAM) that is external to the integrated circuit — the industry-standard implementation of which is DDR DRAM (FIG. 2: element 56 labeled “DRAM”; [0007]: “a bus interface coupled to the set of one or more buses, the bus interface to couple the set of one or more application processors to dynamic random access memory (DRAM) which is external to the integrated circuit”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the front end processing of Lennen (‘354) with the external DDR DRAM storage of Conflitti et al. (‘236). One would have been motivated to do so because Conflitti et al. (‘236) explicitly teaches that external DRAM provides the high bandwidth and storage capacity required to hold GNSS baseband sample data in consumer-grade UE devices, and DDR is the ubiquitous industry-standard implementation of external DRAM in mobile devices. A person of ordinary skill in the art would have had a reasonable expectation of success because the use of external DDR DRAM for high-bandwidth sample storage in mobile GNSS receivers was well established at the time of the invention.
Regarding Claim 3, Lennen (‘354) in view of Conflitti et al. (‘236) teaches the method of claim 1, and further:
Lennen (‘354) teaches: the at least one code-frequency offset combination comprises a plurality of offset combinations; the coherent correlation and accumulation is sequentially performed on the data for each offset combination to generate coherent correlation results for each offset combination; and the coherent correlation results are processed sequentially for each offset combination. Lennen (‘354) teaches a receiver architecture in which a signal processor 406, matched filter 408, coder 410, and carrier and code NCO 412 operate on input samples from RAM 404 for each code-frequency hypothesis in the acquisition search space. The carrier and code NCO 412 generates the carrier and code signals for each hypothesis, and the signal processor 406 extracts, interpolates, and prepares those samples for the matched filter to process each offset combination in turn ([0032]: “Thus, the signal processor 406 extracts the input samples from the RAM 404 and prepares them for use by the matched filter 408. Depending on the mode of the matched filter 408 the input samples will be interpolated and/or decimated to the correct sampling rate for the matched filter 408.”) ([0033]: “The signal processor subsystem 404 may also include a matched filter 408, coder 410, carrier and code numeric coded oscillator (NCO) 412, cross-correlator block 414, cross-correlation removal block 416, and a coherent summation block 418. The signal is processed and specific satellite signals identified. The carrier and code NCO 412 generate the pure carrier and code signals for use by the signal processor 406.”).
Regarding Claims 12 and 19, Lennen (‘354) in view of Conflitti et al. (‘236) teaches the method of claim 1 and the UE of claim 14, respectively, and further:
Lennen (‘354) teaches: the coherent correlation results comprise code-frequency offsets with peak accumulations of correlations over time. Lennen (‘354) teaches that coherent memory 420 stores complex (I, Q) values indexed by code phase tap (code offset) and Doppler frequency bin (frequency offset), representing coherent accumulations of correlations over the integration interval ([0039]–[0040]).
Lennen (‘354) teaches: the non-coherent correlation results comprise code-frequency offsets with peak accumulations of correlations, and code-frequency offset regions of the peak accumulations. Lennen (‘354) teaches that non-coherent memory 432 accumulates magnitude-detected FFT outputs indexed by code-frequency offset, representing peak accumulations of correlations, and that peak sort 814 and detector 428 identify code-frequency offset regions containing correlation peaks ([0041]: “The output of the FFT subsystem 306 may be from the sorter 426 to a detector block 428, from the non-coherent summation of the signal magnitude 424 to the non-coherent RAM 432.”) ([0131]: “The peak sorting occurs 814 where the non-coherent data is sorted by sorter 426 and detection of peaks occurs with detector 428. The detected signals peaks are then stored in ram 430.”).
Regarding Claim 13, Lennen (‘354) in view of Conflitti et al. (‘236) teaches the method of claim 1, and further:
Lennen (‘354) teaches: storing the non-coherent correlation results in a digital signal processing (DSP) random access memory (RAM) of the UE. Lennen (‘354) teaches that non-coherent memory 432, which is a DSP RAM accessible to the correlation processing pipeline, stores the accumulated non-coherent correlation values indexed by code-frequency offset ([0041]: “The output of the FFT subsystem 306 may be … from the non-coherent summation of the signal magnitude 424 to the non-coherent RAM 432.”).
Lennen (‘354) teaches: determining a code offset and a frequency offset for the input based on the non-coherent correlation results. Lennen (‘354) teaches that peak sort 814 and detector 428 search non-coherent memory 432 to determine the code offset and frequency offset at which the peak correlation occurs ([0131]: “The peak sorting occurs 814 where the non-coherent data is sorted by sorter 426 and detection of peaks occurs with detector 428.”).
Regarding Claim 14, Lennen (‘354) in view of Conflitti et al. (‘236) teaches:
Lennen (‘354) teaches: A user equipment (UE) comprising: an input sample memory (ISM) configured to store data from a memory. Lennen (‘354)’s input sample RAM 404 constitutes the ISM, storing digitized satellite signal samples for subsequent processing ([0030]: “The input signal may be divided into digital samples in the input sample processing subsystem 402 with the output being stored in random access (RAM) memory 404. The RAM may be any type of read/write memory that may be written to and read from at a rate to keep data flowing between the input sample subsystem 302 and the signal processing subsystem 304.”).
Lennen (‘354) does not explicitly teach, but Conflitti et al. (‘236) teaches: wherein the data corresponds to input from an L5 antenna of the UE. Lennen (‘354) does not restrict its receiver to the L5 band or explicitly teach that the ISM data originates from an L5 antenna. Conflitti et al. (‘236) teaches a GNSS receiver dedicated to receiving only L5/E5 band signals from an L5 antenna, explicitly excluding L1 (Abstract: “GNSS receivers and systems within such receivers use improvements to reduce memory usage while providing sufficient processing resources to receive and acquire and track E5 band GNSS signals directly (without attempting in one embodiment to receive L1 GNSS signals).”) ([0136]: “The GNSS receiver can include a GNSS radiofrequency (RF) front end 153 which receives GNSS signals through an antenna 151 that is coupled to the GNSS RF front-end 153. In one embodiment, the GNSS RF front end 153 receives only L5 WB GNSS signals.”). The motivation to combine Conflitti et al. (‘236) with Lennen (‘354) is as set forth in claim 1 above.
Lennen (‘354) teaches: a first high-resolution correlation (HRC) engine configured to perform coherent correlation and accumulation on the data for at least one code-frequency offset combination, to generate coherent correlation results. Lennen (‘354)’s matched filter 408 with coder 410 and carrier NCO 412, reading from input sample RAM 404 and writing coherent results to coherent memory 420, constitutes the first HRC engine, as discussed for claim 1 above.
Lennen (‘354) teaches: a second HRC engine configured to process the coherent correlation results by at least performing frequency widening and non-coherent accumulation to generate non-coherent correlation results indicating at least peak accumulations of correlations. Lennen (‘354)’s FFT 422, ABS block 424, and non-coherent memory 432 collectively constitute the second HRC engine performing frequency widening and non-coherent accumulation, as discussed for claim 1 above.
Regarding Claim 15, Lennen (‘354) in view of Conflitti et al. (‘236) teaches the UE of claim 14, and further:
Lennen (‘354) teaches: a front end processor (FEP) configured to process the input from the L5 antenna after conversion into a digital data stream, wherein the processed data is saved at the memory, and the memory comprises an external double data rate (DDR) memory. These apparatus limitations are the apparatus analogs of the corresponding method limitations of claim 2. Lennen (‘354)’s input sample processing subsystem 302 constitutes the FEP ([0029]), and Conflitti et al. (‘236)’s external DRAM 56 (FIG. 10), implemented as DDR in accordance with well-known mobile UE practice, constitutes the external DDR memory. The motivation to combine is as set forth in claim 2 above.
Regarding Claim 16, Lennen (‘354) in view of Conflitti et al. (‘236) teaches the UE of claim 14, and further:
Lennen (‘354) teaches: the at least one code-frequency offset combination comprises a plurality of offset combinations; the coherent correlation and accumulation is sequentially performed on the data for each offset combination to generate coherent correlation results for each offset combination; and the coherent correlation results are processed sequentially for each offset combination. These apparatus limitations are the apparatus analogs of the corresponding method limitations of claim 3 and are taught by the same art for the same reasons. Lennen (‘354)’s sequential hypothesis search architecture across code-phase and Doppler-frequency offset combinations ([0031]–[0033]) and Conflitti et al. (‘236)’s confirmation of that architecture ([0199]) are discussed for claim 3 above.
Regarding Claim 20, Lennen (‘354) in view of Conflitti et al. (‘236) teaches:
Lennen (‘354) in view of Conflitti et al. (‘236) teaches: A user equipment (UE) comprising: a processor; and a non-transitory computer readable storage medium storing instructions that, when executed, cause the processor to: load data from a memory to an input sample memory (ISM) of the UE, wherein the data corresponds to input from an L5 antenna of the UE; perform, by a first high-resolution correlation (HRC) engine of the UE, coherent correlation and accumulation on the data for at least one code-frequency offset combination, to generate coherent correlation results; and process, by a second HRC engine of the UE, the coherent correlation results by at least performing frequency widening and non-coherent accumulation to generate non-coherent correlation results indicating at least peak accumulations of correlations. Claim 20 is a non-transitory computer-readable storage medium claim whose recited operations are substantively identical to the method operations of claim 1. Lennen (‘354) teaches that its receiver processing functions — loading of input samples, coherent correlation and accumulation, and FFT-based frequency widening and non-coherent accumulation — are implemented via processor-executed program instructions stored in memory ([0029]–[0031], [0041], [0131]). All limitations of claim 20 are rendered obvious by the same art and for the same reasons as claim 1 above. The motivation to combine Conflitti et al. (‘236) with Lennen (‘354) is as set forth in claim 1 above.
Claims 4-7 and 17 are rejected under 35 U.S.C. § 103 as being unpatentable over Lennen (US 2010/0134354 A1) in view of Conflitti et al. (US 2022/0137236 A1), further in view of Van Wechel et al. (US 2007/0210958 A1).
Regarding Claim 4, Lennen (‘354) in view of Conflitti et al. (‘236) teaches the method of claim 3, and further:
Lennen (‘354) teaches: storing each of the coherent correlation results at a coherent integration time (CIT) memory of the UE. Lennen (‘354) teaches coherent memory 420, which stores the complex (I, Q) coherent correlation outputs produced by matched filter 408 after each coherent accumulation interval. This coherent memory 420 corresponds to the CIT memory ([0039]: “The coherent buffer 420 may be a first in first out (fifo) buffer that passes blocks of data from the output of a coherent accumulator to the input of the FFT 422.”) ([0040]: “The coherent buffer 420 holds the output of the matched filter 408 as a complex value (I, Q).”).
Lennen (‘354) does not explicitly teach, but Van Wechel et al. (‘958) teaches: wherein one of a first region and a second region of the CIT memory is used for data storage by the first HRC engine while another of the first region and the second region is accessed for data retrieval by the second HRC engine in a ping-pong manner. Lennen (‘354)’s coherent memory 420 is disclosed as a single FIFO buffer ([0039]) — a single-region memory that passes accumulated data from the matched filter to the FFT. Lennen (‘354) does not disclose partitioning the CIT memory into a first region and a second region, nor does Lennen (‘354) disclose an alternating write/read (ping-pong) scheme between the two pipeline stages. Van Wechel et al. (‘958) teaches a GNSS correlator in which multiple coherent integration memory regions alternate between accumulating new coherent correlation data from the upstream correlator and being read out through a multiplexer to the downstream magnitude detector/FFT, with each region’s locations cleared after readout so that the same region can immediately begin accumulating new data. One region is thus written by the first engine while another is read by the second engine, in alternating fashion ([0021]: “One system further staggers the start and stop times of coherent integration of different frequency bins and clears individual memory locations of coherent integration memory as the memory locations are read. The stagger and clearing allow the system to reuse magnitude computation circuits and continue to accumulate coherent data without employing expensive double buffered memory.”) ([0061]: “When reducing acquisition time is important, the amount of input memory is usually doubled in order to allow the FFT to process existing data while allowing the input memory to continue to store new data. Such memories are called double-buffered memories.”) ([0137]: “When the first and second coherent integration memories 912, 914 complete accumulating data, the integrate/dump control 930 commands the multiplexer 924 to couple the first and second coherent integration memories 912, 914 to the magnitude detector 508 … As the contents of the first and second coherent integration memories 912, 914 are read into the magnitude detector 508, the memory locations are cleared (reset of accumulation) so that the first and second coherent integration memories 912, 914 can begin to accumulate new data.”) ([0140]: “By double buffering and doubling the size of the coherent integration memory 928, a single magnitude detector 508 can also be reused to compute the magnitudes of the coherent integration results for all the frequency bins.”) (Claim 1: “an integrate and dump control circuit configured to sequence the start of a plurality of coherent integration memories and sequence the outputs of the plurality of coherent integration memories in sequence, the integrate and dump control circuit further configured to reset a memory location after the memory location has been accessed; and a multiplexer circuit coupled to the plurality of coherent integration memories, the multiplexer circuit configured to select coherent integration memories that are outputting data.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the CIT memory of Lennen (‘354) with the ping-pong coherent integration memory management of Van Wechel et al. (‘958). One would have been motivated to do so because Van Wechel et al. (‘958) expressly identifies the design problem motivating the combination and its solution: in a correlator pipeline where coherent accumulation continuously generates new coherent result blocks while downstream FFT/magnitude processing consumes prior coherent result blocks, dividing the coherent integration memory into two alternating regions enables concurrent accumulation in one region while the other is read out — permitting continuous coherent accumulation, avoiding pipeline dead time, and enabling hardware reuse of the magnitude computation circuit without requiring expensive overall memory duplication (Van Wechel et al. [0061]: “When reducing acquisition time is important, the amount of input memory is usually doubled in order to allow the FFT to process existing data while allowing the input memory to continue to store new data. Such memories are called double-buffered memories.”). In high-throughput GNSS acquisition pipelines such as Lennen (‘354)’s, where coherent accumulation continuously generates new coherent result blocks from matched filter 408 while FFT 422 processes prior coherent result blocks from coherent memory 420, it would have been advantageous to implement the known double-buffered coherent integration memory of Van Wechel et al. (‘958) to permit concurrent accumulation and readout without pipeline interruption and to enable hardware reuse of the magnitude/FFT computation stage. A person of ordinary skill in the art would have had a reasonable expectation of success because Van Wechel et al. (‘958) demonstrates the operability of this technique in a GPS correlator pipeline of the same architectural type as Lennen (‘354) — a matched filter feeding coherent integration memory feeding an FFT/magnitude stage — and because Van Wechel et al. (‘958) explicitly provides a claim directed to the integrate-and-dump control and multiplexer circuit needed to implement this architecture, confirming its known implementability.
Regarding Claim 5, Lennen (‘354) in view of Conflitti et al. (‘236) and further in view of Van Wechel et al. (‘958) teaches the method of claim 4, and further:
Lennen (‘354) does not explicitly teach, but Van Wechel et al. (‘958) teaches: each of the first region and the second region comprises four CIT regions, and each CIT region comprises 320 correlator taps. Lennen (‘354) teaches coherent memory 420 only as a FIFO buffer storing I, Q complex outputs from the matched filter ([0039]: “The coherent buffer 420 may be a first in first out (fifo) buffer that passes blocks of data from the output of a coherent accumulator to the input of the FFT 422.”) ([0040]: “The coherent buffer 420 holds the output of the matched filter 408 as a complex value (I, Q).”). Lennen (‘354) does not disclose organizing that memory into sub-regions defined by a count of correlator taps. Van Wechel et al. (‘958) expressly teaches coherent integration memories organized by correlator tap count, with the tap count per region (N) and the number of frequency bin sub-regions (K) treated as explicit, selectable design parameters that are sized to the requirements of the target acquisition system ([0156]: “In one embodiment, there are 2048 taps (N) and 16 DFT frequency bins.”). Van Wechel et al. (‘958)’s use of the phrase “in one embodiment” for the 2048-tap value affirmatively confirms that N is a configurable parameter — not a fixed architectural constant — and that different tap counts per region are contemplated within the same disclosed architecture. The claimed values of four CIT sub-regions per ping-pong half, each comprising 320 correlator taps, are therefore a routine engineering sizing choice within the general tap-partitioned, ping-pong CIT memory framework disclosed by Van Wechel et al. (‘958), selected based on the code phase search window, PDI duration, FFT block size, and memory bus width of the target implementation. Such sizing decisions are routine design choices for a person of ordinary skill in the art of GNSS, especially when related to correlator hardware. Furthermore, to the extent the specification of the instant application at issue teaches that embodiments are not limited to the recited numerical values, that disclosure itself confirms that the specific values of four sub-regions and 320 taps per sub-region are not a critical, non-obvious contribution beyond the general architectural concept taught by Van Wechel et al. (‘958)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the tap-partitioned, ping-pong CIT memory of Van Wechel et al. (‘958) in the combined Lennen (‘354)/Conflitti et al. (‘236) receiver with a specific number of sub-regions and tap count per sub-region selected to match the acquisition system’s code phase resolution, PDI duration, FFT block size, and memory architecture. One would have been motivated to do so because Van Wechel et al. (‘958) expressly treats the tap count per memory region and the number of frequency bin sub-regions as design parameters to be selected based on system requirements — demonstrating that parameterizing these values is the expected practice, not an inventive act. A person of ordinary skill in the art implementing an L5 GNSS acquisition engine with tap-partitioned coherent integration memory would have applied standard GNSS hardware design practice to select tap count and sub-region count values appropriate to the target system’s search window and memory constraints, arriving at specific numerical values as a matter of routine engineering sizing without the exercise of inventive skill. A person of ordinary skill in the art would have had a reasonable expectation of success because Van Wechel et al. (‘958) demonstrates a working tap-partitioned coherent memory architecture with specific numerical parameters, confirming that such architectures are implementable and that parameter selection is a routine engineering task within the ordinary level of skill.
Regarding Claim 6, Lennen (‘354) in view of Conflitti et al. (‘236) and further in view of Van Wechel et al. (‘958) teaches the method of claim 4, and further:
Lennen (‘354) teaches: processing the coherent correlation results comprises, for each offset combination: performing fast Fourier transform (FFT) on the coherent correlation results to widen a frequency range covered by a respective code-frequency offset. Lennen (‘354) teaches FFT block 422 that transforms the coherent correlation results from coherent memory 420 into the frequency domain, simultaneously evaluating multiple Doppler frequency bins and widening the effective frequency search range per code-frequency hypothesis ([0041]: “The FFT subsystem 306 … may be coupled to the Fast Fourier Transfer (FFT) block 422.”) ([0131]: “The output of the coherent memory 420 is then processed by the FFT 422. The FFT 422 enables short coherent integrations and combines them.”).
Lennen (‘354) teaches: selecting a number of center frequencies from the widened frequency range for the respective code-frequency offset. Lennen (‘354) teaches filter block 424 and sorter block 426 that evaluate the magnitude of each FFT output bin and identify peak frequency bins as candidate center frequencies from the widened range ([0041]: “The output of the FFT subsystem 306 may be from the sorter 426 to a detector block 428, from the non-coherent summation of the signal magnitude 424 to the non-coherent RAM 432.”).
Lennen (‘354) teaches: performing non-coherent accumulation on the FFT coherent correlation results, with respect to the number of center frequencies, to increase an accumulation time and generate the non-coherent correlation results. Lennen (‘354) teaches non-coherent memory 432 that accumulates the magnitude-detected FFT outputs across successive coherent integration intervals for each center frequency, increasing the effective integration time for weak signal detection and generating the non-coherent correlation results ([0131]: “The normalized value from block 424 may be referred to as non-coherent data and is then stored in the non-coherent memory 432.”).
Regarding Claim 7, Lennen (‘354) in view of Conflitti et al. (‘236) and further in view of Van Wechel et al. (‘958) teaches the method of claim 4, and further:
Claim 7 recites two alternatives connected by “or.” Per MPEP § 2143.03, the claim is rendered obvious if the prior art teaches either alternative. Accordingly, only the first alternative need be established.
Lennen (‘354) teaches: the data comprises 1 millisecond (ms) of data. Lennen (‘354) teaches a 4 msec length spreading code for Galileo acquisition and explicitly identifies that a time window of less than or equal to one millisecond is one operative mode ([0137]: “The short code generator may be implemented as 25 bits in memory that are successively clocked out. The 25 bits are effectively data modulated onto the 4 msec length spreading code, so the 25-bit code causes the sequence to repeat every 100 msecs.”) ([0138]: “If a small time window, such as less than or equal to one millisecond is desired, then a 1/s chip search scheme is used with BOC correlation process of 16fo samples.”).
Lennen (‘354) does not explicitly teach, but Conflitti et al. (‘236) teaches: the ISM comprises a 3 ms circular ISM. Lennen (‘354) does not disclose the ISM as a circular buffer or specify its size in milliseconds relative to the code period. Conflitti et al. (‘236) teaches that its baseband sample memory is implemented as a circular buffer storing slightly more than 1 ms of GNSS sample data ([0139]: “the digitized GNSS sample data is stored in a two-dimensional memory array which can be a circular buffer (such as the memory 253 in FIG. 6) containing slightly more than one 1-millisecond frame of GNSS signal data such as 1.05 or 1.25 milliseconds of GNSS signal data.”). Sizing a circular ISM to hold 3 ms of data when processing 1 ms code periods — approximately 3x the code period — provides sufficient buffer depth to allow the correlation engine to read a previously loaded code period while a newer code period continues to load. A person of ordinary skill in the art would have found it obvious to size the circular ISM at approximately 3x the code period for this purpose, and the specific 3 ms sizing for 1 ms L5 data would have been a straightforward engineering selection within the ordinary level of skill.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the circular sample memory buffer architecture of Conflitti et al. (‘236) with the 1 ms L5 acquisition pipeline of Lennen (‘354). One would have been motivated to do so because Conflitti et al. (‘236) explicitly teaches that a circular buffer memory provides the continuous data availability needed to support GNSS correlation processing without interruption — the same processing pipeline present in Lennen (‘354). A person of ordinary skill in the art would have had a reasonable expectation of success because Conflitti et al. (‘236) demonstrates operability of the circular ISM architecture in the same L5 GNSS acquisition context.
Regarding Claim 17, Lennen (‘354) in view of Conflitti et al. (‘236) teaches the UE of claim 16, and further:
Lennen (‘354) teaches: a coherent integration time (CIT) memory configured to store each of the coherent correlation results. Lennen (‘354)’s coherent memory 420 stores the complex (I, Q) coherent correlation outputs from matched filter 408 and corresponds to the CIT memory ([0039]–[0040]), as discussed for claim 4 above.
Lennen (‘354) does not explicitly teach, but Van Wechel et al. (‘958) teaches: wherein one of a first region and a second region of the CIT memory is used for data storage by the first HRC engine while another of the first region and the second region is accessed for data retrieval by the second HRC engine in a ping-pong manner. Lennen (‘354)’s coherent memory 420 is a single FIFO buffer ([0039]) and does not teach the two-region ping-pong structure. Van Wechel et al. (‘958) teaches the missing ping-pong element through its plurality of coherent integration memory regions that alternate between write and read roles under the control of an integrate-and-dump circuit and multiplexer ([0021], [0061], [0137], [0140], Van Wechel Claim 1), as fully set forth in the analysis of claim 4 above, which is incorporated herein by reference. The motivation to combine Van Wechel et al. (‘958) with Lennen (‘354)/Conflitti et al. (‘236) for this element and the reasonable expectation of success are as set forth in claim 4 above.
Lennen (‘354) teaches: wherein processing the coherent correlation results comprises, for each offset combination: performing fast Fourier transform (FFT) on the coherent correlation results to widen a frequency range covered by a respective code-frequency offset; selecting a number of center frequencies from the widened frequency range for the respective code-frequency offset; and performing non-coherent accumulation on the FFT coherent correlation results, with respect to the number of center frequencies, to increase an accumulation time and generate the non-coherent correlation results. These apparatus processing limitations are the apparatus analogs of the method limitations of claim 6 and are taught by Lennen (‘354)’s FFT 422, filter/ABS 424, and non-coherent RAM 432 for the same reasons discussed for claim 6 above.
Claims 8-11 and 18 are rejected under 35 U.S.C. § 103 as being unpatentable over Lennen (US 2010/0134354 A1) in view of Conflitti et al. (US 2022/0137236 A1), further in view of Van Wechel et al. (US 2007/0210958 A1) and Tingting et al. (‘433).
Regarding Claim 8, Lennen (‘354) in view of Conflitti et al. (‘236) and further in view of Van Wechel et al. (‘958) teach the method of claim 7, and further:
Claim 8 recites two alternatives connected by “or.” Per MPEP § 2143.03, the claim is rendered obvious if the prior art teaches either alternative. Only one element — the data comprises the 1 ms of data for strong signal acquisition or the 4 ms of data for weak signal acquisition with a known NH code alignment — need be established.
Lennen (‘354) does not explicitly teach, but Tingting et al. (‘433) teaches: the data comprises the 1 ms of data for strong signal acquisition or the 4 ms of data for weak signal acquisition with a known NH code alignment. Tingting et al. teaches an L5 GNSS signal acquisition method in which the L5 signal is captured using NH-code-aligned coherent integration. Tingting et al. teaches that the L5 signal has a 1 ms pseudo-random code period with different NH codes modulated every millisecond, making direct capture using conventional 1 ms correlation of low sensitivity ([007]: “the pseudo-random code period of the I channel and the Q channel of the L5 signal is only 1 ms, and different NH codes are modulated every millisecond, so the sensitivity of directly capturing using the conventional correlation method is very low.”). Tingting et al. further teaches performing 1 ms coherent integration results for each half-chip code phase candidate, then accumulating those 1 ms results over 20 ms according to the NH code symbol to identify the correct NH code alignment and capture the L5 signal ([0064]: “generating a pseudo-random code of the L5 signal corresponding to the current satellite, and performing cyclic correlation on the resampled data corresponding to each half chip by using a pseudo-random code to obtain a 1 ms coherent integration result corresponding to each half chip; according to the NH code symbol The coherent accumulation of the 1ms coherent integration result corresponding to each half chip is 20ms, and the 20ms coherent accumulation data corresponding to each half chip is obtained.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the NH-boundary-aligned coherent integration scheme of Tingting et al. (‘433) with the L5 acquisition pipeline of Lennen (‘354) in view of Conflitti et al. (‘236). One would have been motivated to do so because Tingting et al. addresses an L5-specific signal processing problem directly applicable to any L5 receiver: the L5 Neumann-Hoffman secondary code at 1 kHz causes destructive cancellation of coherent accumulations that cross an NH code phase boundary, and Tingting et al. teaches that aligning the 4 ms integration window to the NH boundary enables extended coherent integration for weak signal acquisition without that cancellation. A person of ordinary skill in the art would have had a reasonable expectation of success because Tingting et al. demonstrates operability of this technique for L5 acquisition, and all three references address the same L5 signal acquisition context.
Regarding Claim 9, Lennen (‘354) in view of Conflitti et al. (‘236) teach the method of claim 1, and further:
Lennen (‘354) teaches: the at least one code-frequency offset combination comprises a single offset combination. Lennen (‘354) teaches a receiver that processes each code-frequency hypothesis in turn ([0031]–[0033]). When processing one hypothesis at a time, the combination comprises a single offset combination, which Lennen (‘354)’s sequential architecture inherently satisfies.
Lennen (‘354) does not explicitly teach, but Van Wechel et al. (‘958) teaches: storing the coherent correlation results across four CIT regions of a CIT memory of the UE, wherein each CIT region comprises 320 correlator taps. Lennen (‘354) teaches coherent memory 420 only as a FIFO buffer that stores the I, Q complex output of matched filter 408 ([0039]: “The coherent buffer 420 may be a first in first out (fifo) buffer that passes blocks of data from the output of a coherent accumulator to the input of the FFT 422.”) ([0040]: “The coherent buffer 420 holds the output of the matched filter 408 as a complex value (I, Q).”). Lennen (‘354) does not disclose any internal partitioning of the coherent memory into discrete regions, nor does Lennen (‘354) disclose organizing that memory by a defined number of correlator taps per region. Van Wechel et al. (‘958) teaches coherent integration memories explicitly organized into discrete regions each comprising N correlator taps, with multiple such regions corresponding to separate frequency bins ([0156]: “In one embodiment, there are 2048 taps (N) and 16 DFT frequency bins.”). The specific parameters of four CIT regions each comprising 320 correlator taps are engineering design choices within the ordinary level of skill in the art. The L5 signal at 1.023 Mcps sampled at approximately 2 samples per chip yields approximately 2046 samples per 1 ms code period. Partitioning the CIT memory into sub-regions of 320 taps to match available hardware resources or a desired code phase search window, and selecting four such sub-regions to cover the code phase uncertainty range, constitutes routine sizing that a person of ordinary skill in the art would arrive at through standard engineering design practice without the exercise of inventive skill.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the tap-organized, partitioned coherent integration memory regions of Van Wechel et al. (‘958) with the coherent memory 420 of Lennen (‘354). One would have been motivated to do so because Van Wechel et al. (‘958) teaches that organizing coherent integration memory into discrete tap-based regions enables efficient multiplexed access between the upstream correlator and the downstream FFT/magnitude processing stage — the same pipeline structure present in Lennen (‘354)’s architecture between matched filter 408 and FFT 422. A person of ordinary skill in the art would have had a reasonable expectation of success because Van Wechel et al. (‘958) demonstrates operability of tap-partitioned coherent memory organization in a GPS correlator context identical in type to that of Lennen (‘354) and Conflitti et al. (‘236)
Lennen (‘354) does not explicitly teach, but Tingting et al. (‘433) teaches: processing the coherent correlation results comprises, for each of a plurality of NH code alignments: performing fast Fourier transform (FFT) on the coherent correlation results to widen a frequency range covered by a respective code-frequency offset; selecting a number of center frequencies from the widened frequency range for the respective code-frequency offset; and performing non-coherent accumulation on the FFT coherent correlation results, with respect to the number of center frequencies, to increase an accumulation time and generate the non-coherent correlation results. Lennen (‘354) does not disclose iterating coherent correlation result processing over a plurality of NH code alignment hypotheses. Tingting et al. (‘433) teaches iterating over multiple NH code alignment hypotheses — specifically each half-chip position in the code phase search range centered on the estimated NH code boundary value — and for each, performing correlation and coherent accumulation to identify the correct NH code phase ([0059]: “the code phase search range of the L5 signal may specifically be a code phase within a certain range centered on the NH code boundary value of the estimated L5 signal.”) ([0064]: “generating a pseudo-random code of the L5 signal corresponding to the current satellite, and performing cyclic correlation on the resampled data corresponding to each half chip by using a pseudo-random code to obtain a 1 ms coherent integration result corresponding to each half chip; according to the NH code symbol The coherent accumulation of the 1ms coherent integration result corresponding to each half chip is 20ms, and the 20ms coherent accumulation data corresponding to each half chip is obtained.”). The motivation to combine Tingting et al. (‘433) with Lennen (‘354)/Conflitti et al. (‘236) and the reasonable expectation of success are as set forth in claim 8 above.
Regarding Claim 10, Lennen (‘354) in view of Conflitti et al. (‘236) and further in view of Van Wechel et al. (‘958) and Tingting et al. (‘433) teaches the method of claim 9, and further:
Lennen (‘354) does not explicitly teach, but Tingting et al. (‘433) teaches: processing the coherent correlation results comprises, for each of a plurality of NH code alignments, wherein the plurality of NH code alignments comprises NH code alignments for 1ms data. Lennen (‘354) does not disclose iterating coherent correlation result processing over a plurality of NH code alignment hypotheses. Lennen (‘354)’s coherent integration windows are 1 ms intervals aligned to the PN code epoch and are not controlled by or iterated across NH secondary code phase boundaries ([0039]: “The coherent buffer 420 may be a first in first out (fifo) buffer that passes blocks of data from the output of a coherent accumulator to the input of the FFT 422.”).
Tingting et al. (‘433) teaches iterating over multiple NH code alignment candidates — each half-chip position within the code phase search range centered on the NH code boundary — and for each performing 1 ms coherent integration ([0059]: “the code phase search range of the L5 signal may specifically be a code phase within a certain range centered on the NH code boundary value of the estimated L5 signal.”) ([0086]: “The correlator 305 is configured to perform cyclic correlation on the resampled data corresponding to each half chip by using a pseudo random code to obtain a 1 ms coherent integration result corresponding to each half chip.”).
Lennen (‘354) teaches: performing fast Fourier transform (FFT) on the coherent correlation results to widen a frequency range covered by a respective code-frequency offset; selecting a number of center frequencies from the widened frequency range for the respective code-frequency offset; and performing non-coherent accumulation on the FFT coherent correlation results, with respect to the number of center frequencies, to increase an accumulation time and generate the non-coherent correlation results. The inner processing steps within each NH alignment iteration are taught by Lennen (‘354)’s FFT 422, filter/ABS 424, and non-coherent RAM 432 for the same reasons discussed for claim 6 above ([0041]: “The FFT subsystem 306 … may be coupled to the Fast Fourier Transfer (FFT) block 422.”) ([0131]: “The output of the coherent memory 420 is then processed by the FFT 422. The FFT 422 enables short coherent integrations and combines them. The absolute value or normalization of the output of the FFT 422 occurs in block 424. The normalized value from block 424 may be referred to as non-coherent data and is then stored in the non-coherent memory 432.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the NH-alignment-iterated processing of Tingting et al. (‘433) with the L5 acquisition pipeline of Lennen (‘354) in view of Conflitti et al. (‘236). One would have been motivated to do so because Tingting et al. teaches that the L5 Neumann-Hoffman secondary code at 1 kHz causes destructive cancellation of coherent accumulations that cross an NH code phase boundary, and that iterating over NH code alignment candidates is the means by which a receiver identifies the correct NH code phase for weak signal acquisition — a problem directly applicable to any L5 receiver including the combined Lennen (‘354)/Conflitti et al. (‘236) architecture. A person of ordinary skill in the art would have had a reasonable expectation of success because Tingting et al. demonstrates operability of this technique for L5 acquisition, and all three references address the same L5 signal acquisition context.
Regarding Claim 11, Lennen (‘354) in view of Conflitti et al. (‘236) and further in view of Van Wechel et al. (‘958) and Tingting et al. (‘433) teaches the method of claim 9, and further:
Lennen (‘354) does not explicitly teach, but Tingting et al. (‘433) teaches: the data comprises 4 ms of data, and the ISM comprises a 10 ms circular ISM. Lennen (‘354) does not disclose coherent integration over 4 ms of data or an ISM sized to hold 10 ms of data. Lennen (‘354)’s acquisition architecture uses a short code generator for Galileo with a 4 msec spreading code period but does not disclose extending coherent accumulation to 4 ms of input data or sizing the ISM to 10 ms (Lennen [0137]: “The short code generator may be implemented as 25 bits in memory that are successively clocked out. The 25 bits are effectively data modulated onto the 4 msec length spreading code, so the 25-bit code causes the sequence to repeat every 100 msecs.”).
Tingting et al. teaches that the L5 signal has a 1 ms pseudo-random code period with different NH codes modulated every millisecond, and that achieving extended integration sensitivity requires accumulating 1 ms coherent integration results over 20 ms according to the NH code symbol ([0007]: “the pseudo-random code period of the I channel and the Q channel of the L5 signal is only 1 ms, and different NH codes are modulated every millisecond, so the sensitivity of directly capturing using the conventional correlation method is very low.”) ([0064]: “generating a pseudo-random code of the L5 signal corresponding to the current satellite, and performing cyclic correlation on the resampled data corresponding to each half chip by using a pseudo-random code to obtain a 1 ms coherent integration result corresponding to each half chip; according to the NH code symbol The coherent accumulation of the 1ms coherent integration result corresponding to each half chip is 20ms, and the 20ms coherent accumulation data corresponding to each half chip is obtained.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the 4 ms NH-aligned coherent integration and corresponding sample memory sizing of Tingting et al. (‘433) with the L5 acquisition pipeline of Lennen (‘354) in view of Conflitti et al. (‘236). One would have been motivated to do so because Tingting et al. teaches that extending coherent integration to 4 ms aligned to the NH secondary code boundary is the means to achieve weak signal acquisition sensitivity for L5 signals — a problem directly applicable to any L5 receiver including the combined Lennen (‘354)/Conflitti et al. (‘236) architecture. Sizing the circular ISM to hold 10 ms of data when processing a 4 ms coherent integration window is a proportional engineering choice analogous to the 1 ms/3 ms ratio discussed for claim 7, providing sufficient buffer depth for NH-aligned 4 ms coherent integration with simultaneous data loading, and would have been a straightforward design selection within the ordinary level of skill. A person of ordinary skill in the art would have had a reasonable expectation of success because Tingting et al. demonstrates operability of this technique for L5 acquisition, and all three references address the same L5 signal acquisition context.
Regarding Claim 18, Lennen (‘354) in view of Conflitti et al. (‘236), teach the UE of claim 14, and further:
Lennen (‘354) teaches: the at least one code-frequency offset combination comprises a single offset combination. As discussed for claim 9, Lennen (‘354)’s sequential hypothesis-by-hypothesis processing architecture satisfies this limitation.
Lennen (‘354) does not explicitly teach, but Van Wechel et al. (‘958) teaches: storing the coherent correlation results across four CIT regions of a CIT memory of the UE, wherein each CIT region comprises 320 correlator taps. These apparatus limitations are the apparatus analogs of the method limitations of claim 9 regarding the CIT memory structure. Lennen (‘354) does not disclose any internal partitioning of coherent memory 420 into discrete regions nor a defined number of correlator taps per region, as discussed for claim 9 above. Van Wechel et al. (‘958) teaches coherent integration memories organized into discrete regions each comprising N correlator taps ([0156]: “In one embodiment, there are 2048 taps (N) and 16 DFT frequency bins.”). The specific parameters of four CIT regions each comprising 320 correlator taps are routine engineering sizing parameters within the ordinary level of skill, as discussed for claim 9 above. The motivation to combine Van Wechel et al. (‘958) with Lennen (‘354)/Conflitti et al. (‘236) and the reasonable expectation of success are as set forth in claim 9 above.
Lennen (‘354) does not explicitly teach, but Tingting et al. (‘433) teaches: wherein processing the coherent correlation results comprises, for each of a plurality of Neumann Hoffman (NH) code alignments. Lennen (‘354) does not disclose iterating coherent correlation result processing over a plurality of NH code alignment hypotheses, as discussed for claim 10 above. Tingting et al. teaches iterating over multiple NH code alignment candidates — each half-chip position within the code phase search range centered on the NH code boundary — and for each candidate, performing the coherent correlation result processing to identify the correct NH code phase ([0059]: “the code phase search range of the L5 signal may specifically be a code phase within a certain range centered on the NH code boundary value of the estimated L5 signal.”) ([0064]: “generating a pseudo-random code of the L5 signal corresponding to the current satellite, and performing cyclic correlation on the resampled data corresponding to each half chip by using a pseudo-random code to obtain a 1 ms coherent integration result corresponding to each half chip; according to the NH code symbol The coherent accumulation of the 1ms coherent integration result corresponding to each half chip is 20ms, and the 20ms coherent accumulation data corresponding to each half chip is obtained.”). The motivation to combine Tingting et al. with Lennen (‘354)/Conflitti et al. (‘236) and the reasonable expectation of success are as set forth in claim 8 above.
Lennen (‘354) teaches: performing fast Fourier transform (FFT) on the coherent correlation results to widen a frequency range covered by a respective code-frequency offset; selecting a number of center frequencies from the widened frequency range for the respective code-frequency offset; and performing non-coherent accumulation on the FFT coherent correlation results, with respect to the number of center frequencies, to increase an accumulation time and generate the non-coherent correlation results. The inner processing steps within each NH alignment iteration are the apparatus analogs of the method limitations of claim 10 and are taught by Lennen (‘354)’s FFT 422, filter/ABS 424, and non-coherent RAM 432 for the same reasons discussed for claim 6 above ([0041]: “The FFT subsystem 306 … may be coupled to the Fast Fourier Transfer (FFT) block 422.”) ([0131]: “The output of the coherent memory 420 is then processed by the FFT 422. The FFT 422 enables short coherent integrations and combines them. The absolute value or normalization of the output of the FFT 422 occurs in block 424. The normalized value from block 424 may be referred to as non-coherent data and is then stored in the non-coherent memory 432.”).
Conclusion
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/REMASH R GUYAH/Examiner, Art Unit 3648
/RESHA DESAI/Supervisory Patent Examiner, Art Unit 3648