Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments filed on 06/27/26 with respect to amended claims 1-4,19,21-26,34-35,39,41-42 and 46-47 have been considered but are not persuasive.
Claim 20 is canceled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim (s) 1-4, 19, 21-23,25-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuboi et al. (US 2022/0353995 A1) hereinafter Tusobi.
Regarding claim 1, Tsuboi discloses , in Fig.7, a circuit board comprising: an insulating layer (10) including a first area (see first area above exposed portion of 8 in Fig.7) on one surface (110) on which an electronic component (1A) is mounted and a second area ( see second area in area above 111) adjacent to the first area, the electronic component (1A) overlapping the first area in a first direction ( widthwise direction of 1A) and including first and second electrode portions (3,4) opposing each other in a second direction (lengthwise direction of 1A) ; a connection pad (7 and8) disposed in the first area; and a solder resist layer (6) covering the one surface (110) of the insulating layer (10) and having a first opening ( see opening between 6 that is within first area above) exposing the connection pad (see 7 and 8 exposed and free of solder resist), wherein the first opening has a width in a third direction ( see thickness of 6 ) perpendicular to the first direction and the second direction smaller than a width of the electronic component in the third direction (see height of 1A from top to bottom), such that at least a portion of the solder resist layer extends from the second area to the first area (see part of solder resist covers a portion of 7 and 8), and a portion of the insulating layer is exposed from the solder resist layer in the first area ( see 111 exposed from solder resist 6).
Regarding claim 2, Tsuboi discloses, in Fig.7 wherein the solder resist layer includes a first portion disposed in the first area ( see part of 6 disposed on top of 7 and 8) and a second portion disposed in the second area (see 6 that disposed in second area which is area above 111), and the first portion is disposed adjacent to one edge of the connection pad (see 6 that covers top of outer edge of 7 or 8).
Regarding claim 3, Tsuboi discloses wherein the solder resist layer includes a first portion disposed in the first area (see portion of 6 within first area) and a second portion disposed in the second area (see portion of 6 outside of first area), and the first portion is disposed to at least partially overlap the connection pad in a first direction perpendicular to the one surface of the insulating layer ( see from top down view 6 overlaps with 7 and 8 in the first area).
Regarding claim 4, Tsuboi discloses wherein the solder resist layer includes: a second opening opened to expose a portion of the insulating layer in the first area (see opening above 111), and the first opening and the second opening are integrally connected (opening above pad 8 is integral with opening above 111).
Regarding claim 19, Tsuboi discloses, in Fig.7, electronic component package comprising: an insulating layer (10) including a first area and a second area on one surface (see first area and second area described above); an electronic component mounted in the first area (see first area described above) the electronic component (1A) overlapping the first area in a first direction ( widthwise direction of 1A) and including first and second electrode portions (3,4) opposing each other in a second direction (lengthwise direction of 1A) ;, a connection pad disposed in the first area; and a solder resist layer that covers the one surface of the insulating layer, has a first opening (see opening formed by 6 above pad 8) exposing the connection pad (8), and is disposed to support first and second corners of electronic component ( left and right corners of 1A) the first and second corners disposed in a third direction perpendicular to the first direction and the second direction, wherein the first opening (opening above 8 with solder resist 6) of the solder resist layer extends in a region between first and second portions of the solder resist layer ( left most part of 6 and right most part of 6) respectively supporting the first and second corners of the electronic component (see Fig.2B).
Regarding claim 21, Tsuboi discloses, in Fig.7, wherein a height of a lower surface of the electronic component (bottom of 3) from the one surface (110) of the insulating layer along the first direction is higher than the height of the upper surface of the first portion (top surface of 6) from the one surface (110) of the insulating layer along the first direction (top-down direction).
Regarding claim 22, Tsuboi discloses, in Fig.7 wherein the first portion includes a portion that is in direct contact with the electronic component (see top surface of 6 in direct contact with bottom of 4).
Regarding claim 23, Tsuboi discloses further comprising a connection portion (9; Fig.7 arranged to connect the electronic component (1E) and the connection pad (7 and 8) to each other, wherein at least a portion of the connection portion (9) is disposed between the electronic component and the solder resist layer along the first direction (see solder 9 between 6 and 4 in the vertical direction).
Regarding claim 25, Tsuboi discloses wherein the solder resist layer includes: second opening exposing a portion of the insulating layer in the first area ( opening above 111).
Regarding claim 26, Tsuboi discloses, wherein the first opening and the second opening are integrally connected (opening above 7 and 8 are connected to opening above 111).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim (s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuboi as applied to claim 19 above, and further in view of Lee et al. (CN 115151031A) hereinafter Lee.
Regarding claim 24, Tsuboi is silent with respect to wherein the connection pad is embedded in the insulating layer and one surface thereof is exposed from the insulating layer.
Lee discloses a connection pad (125-2;Fig.15) is embedded in the insulating layer ( insulating layer of 114) and one surface thereof is exposed from the insulating layer ( top of 125-2 is exposed from the insulating layer 114).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Lee to modify the connection pad of Tsuboi in order to make an electrical connection to perform circuit operations.
Claim (s) 34-35,39,41-42,46-47 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuboi view of Lee.
Regarding claim 34, Tsuboi discloses , in Fig.7, a circuit board (5) comprising: an insulating layer (10); a connection pad (7,8) and having one surface exposed from the insulating layer (top surface of 7 and 8); a solder resist layer (6) disposed on the insulating layer; and a first electronic component (2) disposed on the insulating layer and connected to the connection pad through a connection portion (9) disposed between the connection pad (7 and 8) and the first electronic component, the first electronic component overlapping the insulating layer in a first direction and including first and second electrode portions opposing each other in a second direction ( see 1A overlapping 10 from top to down direction and the two electrodes 3 and 4 in the left right direction) wherein a portion of the solder resist layer ( portion of 6 that overlaps with bottom surface of 4) overlaps the first electronic component ( bottom surface of 4) in the first direction (see how 4 overlaps with a portion of 6 from top down direction; see Fig.7) the solder resist layer includes a first opening (opening above 8) exposing a portion of the connection pad (8) and a second opening (opening above 111) exposing a portion of the insulating layer (10), the first opening overlaps at least a portion of the first electrode portion (4(and has a width in a third direction (see thickness of 6) perpendicular to the first direction and the second direction smaller than a width of the second opening in the third direction ( see width of 111 between the two pads 7 and 8).
Tsuboi fails to specifically disclose the connection pad at least partially embedded in the insulating layer.
Lee discloses a connection pad (125-2; Fig.15) is embedded in the insulating layer ( insulating layer of 114).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Lee to modify the connection pad of Tsuboi in order to make an electrical connection to perform circuit operations.
Regarding claim 35, Tsuboi discloses wherein the connection portion is disposed in the one opening of the solder resist layer (9 is disposed within the opening of 6;Fig.7).
Regarding claim 39 and 46, Tsuboi discloses, in Fig.9, wherein the solder resist layer includes another opening ( see second opening for 1B and 1C) exposing a plurality of other pads (see pads that connect to 1B and 1C), and the circuit board further comprises a second electronic component disposed on the insulating layer and connected to the plurality of other connection pads through other connection portions disposed in the another opening of the solder resist layer ( see 9 for 1B and 9 for 1C).
Tsuboi fails to specifically disclose the plurality of other pads partially embedded in the insulating layer.
Lee discloses a connection pad (125-2; Fig.15) is embedded in the insulating layer (insulating layer of 114).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Lee to modify the plurality of pad of Tsuboi in order to make an electrical connection to perform circuit operations.
Regarding claim 41, Tsuboi discloses circuit board (5;Fig.7) comprising: an insulating layer (10); first and second connection pads (7,8) each having one surface (top surface of 7 and 8) exposed from the insulating layer; a solder resist layer (6) disposed on the insulating layer; and a first electronic component (2) disposed on the insulating layer and including first and second electrode portions (see 3 and 4) respectively connected to the first and second connection pads (7 and 8) through first and second connection portions (left and right 9) disposed between the first and second connection pads (7 and 8) and the first electronic component (2) , wherein the solder resist layer (6) includes one opening to expose a portion of the insulating layer (see portion 111) which overlaps the first electronic component in a first direction perpendicular to the one surface ( see bottom of 4 overlapping with 6 from top to down view), , the first and second electrode portions each are in contact with the solder resist layer (see 3 and 4 in contact with 7 in Fig.7).
Tsuboi fails to specifically disclose the connection pad at least partially embedded in the insulating layer.
Lee discloses a connection pad (125-2; Fig.15) is embedded in the insulating layer ( insulating layer of 114).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Lee to modify the connection pad of Tsuboi in order to make an electrical connection to perform circuit operations.
Regarding claim 42, Tsuboi discloses, wherein the first and second connection portion are disposed in the one opening of the solder resist layer ( see left and right 9 disposed within opening of 6 in Fig.7).
Regarding claim 47, Tsuboi discloses wherein the first and second connection portions (see left and right 9) are in contact with the solder resist layer (see left and right 9 in contact with 6 in Fig.7).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2847
