Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of claims 1-4,19-26,34,35,39,41,42,46-47 in the reply filed on 03/13/2026 is acknowledged. The traversal is on the ground(s) that there isn’t an ultra burden to examine the other species. This is not found persuasive because the structural features of the different species will require different search terms in various classifications. Thousands of references must be reviewed for consideration due to the different structure features of the different species.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim (s) 1-4, 19-23,25-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuboi et al. (US 2022/0353995 A1) hereinafter Tusobi.
Regarding claim 1, Tsuboi discloses , in Fig.2A, a circuit board comprising: an insulating layer (10) including a first area (see first area in Reproduced Fig.2A above) on one surface (110) on which an electronic component (1A) is mounted and a second area ( see second area in Reproduced Fig.2A above) adjacent to the first area; a connection pad (7 and8) disposed in the first area; and a solder resist layer (6) covering the one surface (110) of the insulating layer (10) and being opened to expose the connection pad (see 7 and 8 exposed and free of solder resist), wherein at least a portion of the solder resist layer extends from the second area to the first area (see part of solder resist covers a portion of 7 and 8), and a portion of the insulating layer is exposed from the solder resist layer in the first area ( see 111 exposed from solder resist 6).
Regarding claim 2, Tsuboi discloses, in Fig.2A wherein the solder resist layer includes a first portion disposed in the first area ( see part of 6 disposed on top of 7 and 8) and a second portion disposed in the second area (see 6 that disposed in second area in Rep.Fig2A), and the first portion is disposed adjacent to one edge of the connection pad (see 6 that covers top of outer edge of 7 or 8).
Regarding claim 3, Tsuboi discloses wherein the solder resist layer includes a first portion disposed in the first area (see portion of 6 within first area) and a second portion disposed in the second area (see portion of 6 outside of first area), and the first portion is disposed to at least partially overlap the connection pad in a first direction perpendicular to the one surface of the insulating layer ( see from top down view 6 overlaps with 7 and 8 in the first area).
Regarding claim 4, Tsuboi discloses wherein the solder resist layer includes: a first opening opened to expose at least a portion of the connection pad (see opening directly above and exposing 7 or 8), and a second opening opened to expose a portion of the insulating layer in the first area (see opening above 111), and the first opening and the second opening are integrally connected.
Regarding claim 19, Tsuboi discloses, in Fig.2A, electronic component package comprising: an insulating layer (10) including a first area and a second area on one surface (see first area and second area above in Rep.Fig.2A); an electronic component mounted in the first area (see first area above in Rep.Fig.2A), a connection pad disposed in the first area; and a solder resist layer that covers the one surface of the insulating layer, is opened to expose the connection pad, and is disposed to support the electronic component.
Regarding claim 20, Tsuboi discloses, in Fig.7, wherein the solder resist layer (6) includes a first portion (portion of 6 that is directly underneath 3 or 4) that is disposed to overlap the electronic component (3 and 4) in a first direction perpendicular ( top down direction) to the one surface (110) of the insulating layer to support the electronic component (2,3,4).
Regarding claim 21, Tsuboi discloses, in Fig.7, wherein a height of a lower surface of the electronic component (bottom of 3) from the one surface (110) of the insulating layer along the first direction is higher than the height of the upper surface of the first portion (top surface of 6) from the one surface (110) of the insulating layer along the first direction (top-down direction).
Regarding claim 22, Tsuboi discloses, in Fig.7 wherein the first portion includes a portion that is in direct contact with the electronic component (see top surface of 6 in direct contact with bottom of 4).
Regarding claim 23, Tsuboi discloses further comprising a connection portion (9; Fig.7 arranged to connect the electronic component (1E) and the connection pad (7 and 8) to each other, wherein at least a portion of the connection portion (9) is disposed between the electronic component and the solder resist layer along a first direction perpendicular to the one surface of the insulating layer (see solder 9 between 6 and 4 in the vertical direction).
Regarding claim 25, Tsuboi discloses wherein the solder resist layer includes: a first opening opened to expose at least a portion of the connection pad (opening above 7 and 8) , and a second opening opened to expose a portion of the insulating layer in the first area ( opening above 111).
Regarding claim 26, Tsuboi discloses, wherein the first opening and the second opening are integrally connected (opening above 7 and 8 are connected to opening above 111).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim (s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuboi as applied to claim 19 above, and further in view of Lee et al. (CN 115151031A) hereinafter Lee.
Regarding claim 24, Tsuboi is silent with respect to wherein the connection pad is embedded in the insulating layer and one surface thereof is exposed from the insulating layer.
Lee discloses a connection pad (125-2;Fig.15) is embedded in the insulating layer ( insulating layer of 114) and one surface thereof is exposed from the insulating layer ( top of 125-2 is exposed from the insulating layer 114).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Lee to modify the connection pad of Tsuboi in order to make an electrical connection to perform circuit operations.
Claim (s) 34-35,39,41-42,46-47 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuboi view of Lee.
Regarding claim 34, Tsuboi discloses , in Fig.7, a circuit board (5) comprising: an insulating layer (10); a connection pad (7,8) and having one surface exposed from the insulating layer (top surface of 7 and 8); a solder resist layer (6) disposed on the insulating layer; and a first electronic component (2) disposed on the insulating layer and connected to the connection pad through a connection portion (9) disposed between the connection pad (7 and 8) and the first electronic component, wherein a portion of the solder resist layer ( portion of 6 that overlaps with bottom surface of 4) overlapping the first electronic component ( bottom surface of 4) in a first direction perpendicular to the one surface includes one opening to expose a portion of the insulating layer ( opening eposes 111).
Tsuboi fails to specifically disclose the connection pad at least partially embedded in the insulating layer.
Lee discloses a connection pad (125-2; Fig.15) is embedded in the insulating layer ( insulating layer of 114).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Lee to modify the connection pad of Tsuboi in order to make an electrical connection to perform circuit operations.
Regarding claim 35, Tsuboi discloses wherein the connection portion is disposed in the one opening of the solder resist layer (9 is disposed within the opening of 6;Fig.7).
Regarding claim 39 and 46, Tsuboi discloses, in Fig.9, wherein the solder resist layer includes another opening ( see second opening for 1B and 1C) exposing a plurality of other pads (see pads that connect to 1B and 1C), and the circuit board further comprises a second electronic component disposed on the insulating layer and connected to the plurality of other connection pads through other connection portions disposed in the another opening of the solder resist layer ( see 9 for 1B and 9 for 1C).
Tsuboi fails to specifically disclose the plurality of other pads partially embedded in the insulating layer.
Lee discloses a connection pad (125-2; Fig.15) is embedded in the insulating layer (insulating layer of 114).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Lee to modify the plurality of pad of Tsuboi in order to make an electrical connection to perform circuit operations.
Regarding claim 41, Tsuboi discloses circuit board (5;Fig.7) comprising: an insulating layer (10); a connection pad (7,8) having one surface (top surface of 7 and 8) exposed from the insulating layer; a solder resist layer (6) disposed on the insulating layer; and a first electronic component (2) disposed on the insulating layer and connected to the connection pad (7 and 8) through a connection portion (9) disposed between the connection pad (7 and 8) and the first electronic component (2) , wherein the solder resist layer (6) includes one opening to expose a portion of the insulating layer (see portion 111) which overlaps the first electronic component in a first direction perpendicular to the one surface ( see bottom of 4 overlapping with 6 from top to down view), and in the first direction perpendicular to the one surface ( top down direction ), a lower surface of the first electronic component is above an upper surface of the solder resist layer (lower surface of 2 is above the top surface of 6).
Tsuboi fails to specifically disclose the connection pad at least partially embedded in the insulating layer.
Lee discloses a connection pad (125-2; Fig.15) is embedded in the insulating layer ( insulating layer of 114).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Lee to modify the connection pad of Tsuboi in order to make an electrical connection to perform circuit operations.
Regarding claim 42, Tsuboi discloses, wherein the connection portion is disposed in the one opening of the solder resist layer ( see 9 disposed within opening of 6 in Fig.7).
Regarding claim 47, Tsuboi discloses wherein the connection portion is in contact with the solder resist layer (see 9 in contact with 6 in Fig.7).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2848
Prosecution Insights