DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 9 and 19.
Pending: 1-20.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 5/2/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: GATE-ALL-AROUND TRANSISTOR DEVICE WITH MULTI-LAYER BLOCKING DIELECTRIC STRUCTURE.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chang et al., US PG pub. 20230113269 A1; in view of Lee et al., US PG pub. 20210358910 A1.
Re: Independent Claim 1, Chang discloses a first source/drain pattern (right side 168a in region P-1 and left side 168b in region P-2, fig. 8);
a second source/drain pattern (left side 168a in region P-1 and right side 168b in region N-2, fig. 8) and a third source/drain pattern (middle 168b in region P2, fig. 8) adjacent to the first source/drain pattern (right side 168a in region P-1 and left side 168b in region P-2, fig. 8);
a plurality of semiconductor patterns (108b, fig. 8) between the first source/drain pattern (right side 168a in region P-1 and left side 168b in region P-2, fig. 8) and the third source/drain pattern (middle 168b in region P2, fig. 8);
a gate dielectric layer (182b, fig. 8) in contact with the plurality of semiconductor patterns (108b, fig. 8);
a gate electrode (184b, fig. 8; ¶0119 include one or more layers of conductive material) in contact with the gate dielectric layer (182b, fig. 8);
a plurality of blocking semiconductor patterns (108a, fig. 8) between the first source/drain pattern (right side 168a in region P-1 and left side 168b in region P-2, fig. 8) and the second source/drain pattern (left side 168a in region P-1 and right side 168b in region N-2, fig. 8);
a blocking dielectric layer (182a, fig. 8) in contact with the plurality of blocking semiconductor patterns (108a, fig. 8); and
a blocking electrode (184a, fig. 8) in contact with the blocking dielectric layer (182a, fig. 8),
wherein the blocking dielectric layer (182a, fig. 8) include one or more layers of a dielectric material (¶0118).
Chang is silent regarding: wherein the blocking dielectric layer (182a, fig. 8) includes a first layer in contact with the first source/drain pattern (right side 168a in region P-1 and left side 168b in region P-2, fig. 8) and the second source/drain pattern (left side 168a in region P-1 and right side 168b in region N-2, fig. 8), a second layer in contact with the blocking electrode (184a, fig. 8), and a third layer between the first layer and the second layer, and
wherein a dielectric material in the third layer is different from a dielectric material of the first layer and a dielectric material of the second layer.
Lee discloses wherein the blocking dielectric layer (WF6 of the TR6, fig. 2B) includes a first layer (outer W1, fig. 2B) in contact with the first source/drain pattern (left side SD1 of TR6, fig. 2B) and the second source/drain pattern (right side SD1 of TR6, fig. 2B), a second layer (inner W1 of TR6, fig. 2B) in contact with the blocking electrode (W3, fig. 2B), and a third layer (W2, fig. 2B) between the first layer (outer W1 of TR6, fig. 2B) and the second layer (inner W1 of TR6, fig. 2B), and wherein a dielectric material in the third layer (W2, fig. 2B; ¶0054) is different from a dielectric material of the first layer (outer W1 of TR6, fig. 2B; ¶0051) and a dielectric material of the second layer (inner W1 of TR6, fig. 2B;¶0051).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include multiple layer of blocking dielectric layer since this can improve by reducing gate induced leakage, subthreshold leakage and overall static power.
Re: Claim 2, Chang and Lee discloses all the limitations of claim 1 on which this claim depends. Lee further discloses: wherein the first layer and the second layer include oxide (¶0051), and the third layer includes nitride (¶0054).
Re: Claim 3, Chang and Lee discloses all the limitations of claim 1 on which this claim depends. Chang is silent regarding: wherein a thickness of the blocking dielectric layer (182a, fig. 8) is greater than a thickness of the gate dielectric layer (182b, fig. 8).
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the memory device of Chang that thickness of the blocking dielectric layer is greater than a thickness of the gate dielectric layer as shown in Lee that the blocking dielectric layer can have a thickness greater than the gate dielectric since modification would have only involved a mere change in working range which involves only routine skill in the art one would have been motivated to make such modification to make those layer to have a thinner thickness to achieve the predictable result of miniaturization the memory device thereby improving the prevention of current leakage.
Re: Claim 4, Chang and Lee discloses all the limitations of claim 1 on which this claim depends. Chang further discloses: wherein the blocking electrode (184a, fig. 8) includes:
a first blocking electrode (184a, fig. 8) part over the plurality of blocking semiconductor patterns (108a, fig. 8); and
a second blocking electrode (184a, fig. 8) part between the plurality of blocking semiconductor patterns (108a, fig. 8).
Re: Claim 5, Chang and Lee discloses all the limitations of claim 4 on which this claim depends. Chang is silent regarding: wherein a width of the first blocking electrode (184a, fig. 8) part is less than a width of a part of the gate electrode (184b, fig. 8; ¶0119 include one or more layers of conductive material) over the plurality of semiconductor patterns (108b, fig. 8).
Lee teaches the blocking electrode W3 in TR6 region is less width than gate electrode W3 in TR5 region.
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the memory device of Chang that thickness blocking electrode is less width than gate electrode as shown in Lee’s blocking electrode W3 and Lee’s gate electrode W3 since modification would have only involved a mere change in working range which involves only routine skill in the art one would have been motivated to make such modification to make those layer to have a thinner thickness to achieve the predictable result of miniaturization the memory device thereby having a thinner block electrode can improving the prevention of current leakage.
Re: Claim 6, Chang and Lee discloses all the limitations of claim 1 on which this claim depends. Chang is silent regarding: a blocking electrode (184a, fig. 8) contact in contact with the blocking electrode (184a, fig. 8).
Lee teaches blocking electrode contact (EL6, fig. 2B) contact in contact with the blocking electrode (W3, fig. 2B).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include electrode contact electrically connected to the blocking electrode since the electrode pattern EL6 provide a low resistance and easier access to the gate conductor below.
Re: Claim 7, Chang and Lee discloses all the limitations of claim 1 on which this claim depends. Chang is silent regarding: wherein the gate electrode (184b, fig. 8; ¶0119 include one or more layers of conductive material) includes a first electrode layer in contact with the gate dielectric layer (182b, fig. 8); and a second electrode layer in contact with the first electrode layer.
Lee teaches first electrode layer (WF3, fig. 2B) in contact with the gate dielectric layer (GI, fig. 2B) and a second electrode layer (EL6, fig. 2B) in contact with the first electrode layer (WF3, fig. 2B).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include electrode contact electrically connected to the blocking electrode since the electrode pattern EL6 provide a low resistance and easier access to the gate conductor below.
Re: Claim 8, Chang and Lee discloses all the limitations of claim 7 on which this claim depends. Lee further discloses: wherein a conductive material in the second electrode layer (EL6, fig. 2B; ¶0040) is the same as a conductive material (material: titanium) of the blocking electrode (WF3, fig. 2b;¶0054).
Claim(s) 9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chang et al., US PG pub. 20230113269 A1;in view of Lin et al., US PG pub. 20240395812 A1.
Re: Independent Claim 9, Chang discloses a first source/drain pattern (right side 168a in region P-1 and left side 168b in region P-2, fig. 8); a second source/drain pattern (left side 168a in region P-1 and right side 168b in region N-2, fig. 8) and a third source/drain pattern (middle 168b in region P2, fig. 8) adjacent to the first source/drain pattern (right side 168a in region P-1 and left side 168b in region P-2, fig. 8); a plurality of semiconductor patterns (108b, fig. 8) between the first source/drain pattern (right side 168a in region P-1 and left side 168b in region P-2, fig. 8) and the third source/drain pattern (middle 168b in region P2, fig. 8); a gate dielectric layer (182b, fig. 8) in contact with the plurality of semiconductor patterns (108b, fig. 8); a gate electrode (184b, fig. 8; ¶0119 include one or more layers of conductive material) in contact with the gate dielectric layer (182b, fig. 8); a plurality of blocking semiconductor patterns (108a, fig. 8) between the first source/drain pattern (right side 168a in region P-1 and left side 168b in region P-2, fig. 8) and the second source/drain pattern (left side 168a in region P-1 and right side 168b in region N-2, fig. 8); a blocking dielectric layer (182a, fig. 8) in contact with the plurality of blocking semiconductor patterns (108a, fig. 8); and a first blocking electrode (184a, fig. 8) in contact with the blocking dielectric layer (182a, fig. 8).
Chang is silent regarding: wherein a dielectric material (¶0118) in the blocking dielectric layer (182a, fig. 8) is different from a dielectric material of the gate dielectric layer (182b, fig. 8).
Lin teaches the use of different gate dielectric that can be use for blocking dielectric (244, fig. 35B;¶0061, high-k dielectric material) and gate dielectric layer (242, fig. 35B; ¶0060 silicon oxide).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include different gate dielectric layer since high-k dielectric material can prevent leakage and silicon oxide prove the perfect low interface traps which can improve reliability.
Re: Claim 11, Chang and Lin discloses all the limitations of claim 9 on which this claim depends. Chang further discloses: wherein the blocking dielectric layer (182a, fig. 8) is in contact with top surfaces of the plurality of blocking semiconductor patterns (108a, fig. 8) and bottom surfaces of the plurality of blocking semiconductor patterns (108a, fig. 8).
Re: Claim 12, Chang and Lin discloses all the limitations of claim 9 on which this claim depends. Chang further discloses: a plurality of gate spacers (156a/166a, fig. 8) overlapping the plurality blocking semiconductor patterns (108a, fig. 8),
wherein the blocking dielectric layer (182a, fig. 8) is in contact with the plurality of gate spacers (156a/166a, fig. 8).
Re: Claim 14, Chang and Lin discloses all the limitations of claim 9 on which this claim depends. Chang further discloses: a first active pattern (104-1, fig. 1) overlapping the first blocking electrode (184a, fig. 8); a second active pattern (104-2, fig. 1) spaced apart from the first active pattern (104-1, fig. 1); a second blocking electrode (184a, fig. 8) overlapping the second active pattern (104-2, fig. 1); and a blocking electrode (184a, fig. 8) separation layer between the first blocking electrode (184a, fig. 8) and the second blocking electrode (184a, fig. 8).
Re: Claim 15, Chang and Lin discloses all the limitations of claim 14 on which this claim depends. Chang is silent regarding: wherein a negative voltage is applied to the first blocking electrode (184a, fig. 8), and a positive voltage is applied to the second blocking electrode (184a, fig. 8).
However, although these limitations have been considered by the Examiner, they pertain to the manner in which the device operates. It has been held that a claim containing a recitation pertaining to the manner of operation is not deemed to patentably distinguish the claimed device from a prior art device that is structurally identical. The device of Chang is structurally identical to the Applicant s claimed device. In addition, since the only distinction between the Applicant's claimed device and Chang's is recited in functional language, it is incumbent upon the Applicant to demonstrate that Chang's device is not capable of operating as claimed. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that such functional distinctions do not confer patentability when compared with prior art devices like Chang’s.
Re: Claim 16, Chang and Lin discloses all the limitations of claim 15 on which this claim depends. Chang is silent regarding: wherein the first, second, and third source/drain patterns (168a/168b, fig. 8) include p-type impurities.
However Chang teaches in paragraph 105 166a and 166b can be P-type or N-type dependent on which device is desired. In addition to the conclusion that the prior art element is an equivalent, examiners should also demonstrate, where appropriate, why it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute applicant's described structure, material, or acts for that described in the prior art reference. See In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972). The burden then shifts to applicant to show that the element shown in the prior art is not an equivalent of the structure, material or acts disclosed in the application. In re Mulder, 716 F.2d 1542, 219 USPQ 189 (Fed. Cir. 1983). No further analysis of equivalents is required of the examiner until applicant disagrees with the examiner’s conclusion, and provides reasons why the prior art element should not be considered an equivalent. Therefore, it would have been obvious to one having ordinary skill in the art at that time the invention was made to have the P-region to be N-region for the purpose of the pn-region can be interchangeable.
Re: Claim 17, Chang and Lin discloses all the limitations of claim 9 on which this claim depends. Chang further discloses: wherein a first part of the blocking dielectric layer (182a, fig. 8) is over the plurality of blocking semiconductor patterns (108a, fig. 8), and
a second part of the blocking dielectric layer (182a, fig. 8) is between the plurality of blocking semiconductor patterns (108a, fig. 8).
Re: Claim 18, Chang and Lin discloses all the limitations of claim 17 on which this claim depends. Chang further discloses: wherein the first part of the blocking dielectric layer (182a, fig. 8) has a U shape.
Claim(s) 10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chang et al., US PG pub. 20230113269 A1;in view of Lin et al., US PG pub. 20240395812 A1; further in view of Lee et al., US PG pub. 20210358910 A1.
Re: Claim 10, Chang and Lin discloses all the limitations of claim 17 on which this claim depends. Chang and Lin are silent regarding: wherein the blocking dielectric layer (182a, fig. 8) includes: a first layer in contact with the first source/drain pattern (right side 168a in region P-1 and left side 168b in region P-2, fig. 8) and the second source/drain pattern (left side 168a in region P-1 and right side 168b in region N-2, fig. 8); a second layer in contact with the first blocking electrode (184a, fig. 8); and a third layer between the first layer and the second layer, wherein a dielectric material in the third layer includes is different from a dielectric material of the first layer, a dielectric material of the second layer, and the dielectric material of the gate dielectric layer (182b, fig. 8).
Lee discloses wherein the blocking dielectric layer (WF6 of the TR6, fig. 2B) includes a first layer (outer W1, fig. 2B) in contact with the first source/drain pattern (left side SD1 of TR6, fig. 2B) and the second source/drain pattern (right side SD1 of TR6, fig. 2B), a second layer (inner W1 of TR6, fig. 2B) in contact with the blocking electrode (W3, fig. 2B), and a third layer (W2, fig. 2B) between the first layer (outer W1 of TR6, fig. 2B) and the second layer (inner W1 of TR6, fig. 2B), and wherein a dielectric material in the third layer (W2, fig. 2B; ¶0054) is different from a dielectric material of the first layer (outer W1 of TR6, fig. 2B; ¶0051) and a dielectric material of the second layer (inner W1 of TR6, fig. 2B;¶0051).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include multiple layer of blocking dielectric layer since this can improve by reducing gate induced leakage, subthreshold leakage and overall static power.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Liaw US PG pub. 20210098338 A1”) Discloses a semiconductor structure is provided. The semiconductor structure includes a first well region over a substrate, and an isolation structure over the first well region. The semiconductor structure also includes a first transistor over the first well region, and a first buried conductive line over the first well region and electrically connected to a source structure of the first transistor. A top surface of the first buried conductive line is substantially level with or lower than a top surface of the isolation structure.
* (“Kang et al., US PG pub. 20220199798 A1”) discloses a semiconductor device includes a substrate that includes a peripheral region, a first active pattern on the peripheral region, a first source/drain pattern on the first active pattern, a first channel pattern formed on the first active pattern and connected to the first source/drain pattern, wherein the first channel pattern includes semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode that extends in a first direction and crosses the first channel pattern, a gate insulating layer interposed between the first gate electrode and the first channel pattern, a first gate contact disposed on the first gate electrode and that extends in the first direction, and a first dielectric layer interposed between the first gate electrode and the first gate contact. The first dielectric layer is interposed between the first gate contact and the first gate electrode and extends in the first direction.
Allowable Subject Matter
Claims 19 and 20 are allowed.
Re: Independent Claim 19 (and its dependent claim(s) 20), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: a blocking dielectric layer in contact with the blocking semiconductor patterns; a blocking electrode in contact with the blocking dielectric layer; a blocking electrode contact electrically connected to the blocking electrode; a plurality of gate spacers in contact with the blocking dielectric layer; a gate capping pattern in contact with the blocking dielectric layer and a top surface of the blocking electrode; and an active contact electrically connected to a corresponding one of the first source/drain pattern, the second source/drain pattern, and the third source/drain pattern, wherein the blocking dielectric layer includes a first layer, a second layer, and a third layer, the first layer is in contact with the first source/drain pattern, the second source/drain pattern, and the plurality of blocking semiconductor patterns, the second layer is in contact with the blocking electrode, the third layer is between the first layer and the second layer, the first layer and the second layer include oxide, and the third layer includes nitride.
Claim(s) 13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 13, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: a blocking dielectric layer in contact with the plurality of blocking semiconductor patterns; and a first blocking electrode in contact with the blocking dielectric layer, wherein a dielectric material in the blocking dielectric layer is different from a dielectric material of the gate dielectric layer, a plurality of gate spacers overlapping the plurality blocking semiconductor patterns, wherein the blocking dielectric layer is in contact with the plurality of gate spacers a gate capping pattern between the plurality of gate spacers, wherein the gate capping pattern is in contact with the blocking dielectric layer and the first blocking electrode.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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