DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, the limitation “a first channel structure including…(iii) a channel recess extending into a portion of the first dielectric layer” would raise a new matter issue since the specification of the instant application does not fully and clearly describe such limitation. Applicant alleges that support for such amendments is in Fig. 4 (Remarks dated 08/28/2026, pages 2-3). While Figs. 4 and 22 show a first channel structure CH1 including a channel recess 320R formed by etching a portion of the first dielectric layer 142 (see Fig. 22 and paragraph 232 disclosing “Referring to FIG. 22, a portion of the first dielectric layer 142 exposed by the first expansion hole EH1 may be etched to form a channel recess 320R”), the channel recess 320R is not extending into a portion of the first dielectric layer 142 as claimed (see Figs. 4 and 22) [underlying for clarity]. Instead, Figs. 4 and 22 rather show that the channel recess 320R is on an upper surface of the etched first dielectric layer 142 (see Fig. 22 and paragraph 235 disclosing “Accordingly, a portion of the first dielectric layer 142 may be etched to form a channel recess 320R…the upper surface of the first dielectric layer 142 may be exposed by the channel recess 320R”). As such, the amended limitation as discussed above would raise the new matter issue.
Claims 14 and 19 reciting “a first channel structure including…(iii) a channel recess extending into a portion of the first dielectric layer” are rejected with the same reason for rejecting claim 1 as discussed above. Claims 2-13, 15-18, and 20, which depend from claims 1, 14, and 19, are also rejected by virtue of their dependencies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kashima (US 2020/0286910 A1) in view of Ryu et al. (US 2021/0143160 A1; hereinafter “Ryu”).
Regarding claim 1, referring to Figs. 4, 22, and 23B, Kashima teaches a semiconductor device comprising: a substrate (20) (paragraph 65); a stacked structure including a plurality of gate electrodes (23) stacked on the substrate and spaced apart from each other (paragraphs 67-68); a first channel structure (LP of MP) including (i) a first channel layer (31) extending through the stacked structure and extending along a direction (a z-direction), (ii) a first dielectric layer (32) positioned between the first channel layer and the stacked structure, and (iii) a channel recess extending into a portion of the first dielectric layer ((1) see the rejection of the claim under 35 U.S.C. 112(a) as discussed above and (2) the limitation “(iii) a channel recess extending into a portion of the first dielectric layer” is considered as a channel recess extending on an upper surface of the first dielectric layer and (3) Kashima in Fig. 23B shows a recessed region on an upper surface of 32 where 41’b is formed thereon) (see an annotated Fig. 23B below for “a channel recess” and paragraphs 70-74, 89-90, and 99); an insulating pattern (55) positioned on the stacked structure (paragraph 111); a selection gate electrode (24) positioned on the insulating pattern (paragraph 68); and a second channel structure (UP of MP) connected to the first channel structure (LP) through the selection gate electrode and the insulating pattern (paragraphs 68-71), the second channel structure including a second channel layer (41) extending along the direction (paragraphs 79 and 99), wherein the second channel layer includes: a first portion (a top portion of 41 through 24) extending through the selection gate electrode (Figs. 22 and 23B); a second portion (a middle portion of 41 including a top portion of 41’b through 55, wherein the top portion of 41’b is contacting a top surface of 31) extending through the insulating pattern and contacting an upper surface of the first channel layer (Figs. 22 and 23B); a third portion (a bottom portion of 41 including a bottom portion of 41’b protruding from a bottom surface of the middle portion of 41, and contacting an outer surface of 31) protruding from a lower surface of the second portion, wherein the bottom portion of 41’b is contacting an outer surface of the first channel layer (Figs. 22 and 23B), and wherein the third portion fills the channel recess (41’b partially fills the channel recess) (see the annotated Fig. 23B below).
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Kashima does not explicitly teach that the first dielectric layer (32) includes a first ferroelectric layer. Ryu teaches a semiconductor device (100) comprising: a channel structure (CH) including a channel layer (140) and a first dielectric layer including a first ferroelectric layer (145 including 144 formed of HfSiO) between the channel layer and a gate electrode (130) in order to provide the high-k dielectric material for reducing leakage current from the gate electrode (Figs. 4A-4C and paragraphs 39 and 49-50). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Kashima with that of Ryu in order to provide the high-k dielectric material for reducing leakage current from the gate electrode.
Regarding claim 2, Kashima in view of Ryu teaches wherein a width of the third portion in a radial direction from a center of the first channel structure is greater than a width of the first ferroelectric layer in the radial direction (Kashima, Fig. 23B, the bottom portion of 41’b in a radial direction is greater than a width of 32 and Ryu for the first ferroelectric layer).
Regarding claim 4, Kashima in view of Ryu teaches wherein a thickness of the insulating pattern in the direction (a thickness of 55 in the z-direction) is greater than or equal to a width of the first ferroelectric layer in a radial direction from a center of the first channel structure (a width of 32 in a y-direction) (Kashima, Fig. 22 and Ryu for the ferroelectric material).
Regarding claim 5, Kashima teaches wherein a thickness of the second portion in the direction (a thickness of the middle portion of 41 including the top portion of 41’b in the z-direction) is equal to a width of the third portion in the radial direction from the center of the first channel structure (a width of the bottom portion of 41’b in a y-direction) (Fig. 23B).
Regarding claim 6, Kashima teaches wherein at least a portion of the third portion does not overlap the second portion in the direction (Fig. 23B).
Regarding claim 7, Kashima teaches wherein at least a portion of the first channel structure overlaps the second channel structure in the direction (Fig. 22).
Regarding claim 8, Kashima in view of Ryu teaches wherein a first side portion of the first ferroelectric layer (a left-side portion of 32 shown in Fig. 23B) is in contact with the second channel layer, and a second side portion of the first ferroelectric layer (a right-side portion of 32 shown in Fig. 23B) is in contact with the insulating pattern (Kashima, Fig. 23B and Ryu for the ferroelectric material).
Regarding claim 9, Kashima teaches further comprising: a cell region insulating layer (54) positioned between the insulating pattern and the stacked structure and covering an upper surface of the stacked structure and a side surface of the first channel structure (Fig. 22 and paragraph 103), wherein a first side portion of the second portion overlaps the cell region insulating layer in the direction, and a second side portion of the second portion overlaps the first channel structure in the direction (Figs. 22-23B).
Regarding claim 10, Kashima does not explicitly teach that a thickness of the selection gate electrode is greater than a thickness of the gate electrode and a material difference between the selection gate electrode and the gate electrode. Ryu teaches a semiconductor device (100) comprising: gate electrodes (130) and a selection gate electrode (150), wherein a thickness of the selection gate electrode (a thickness of 150) in a direction (a z-direction) is greater than a thickness of each of the gate electrodes (a thickness of each gate of 130) in the direction (Fig. 4A), and the selection gate electrode includes a different material (for example, 130 formed of a metal material) from a material of the gate electrodes (for example, 150 formed of a semiconductor material) (Fig. 4A and paragraphs 45 and 55). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Kashima with that of Ryu in order to obtain the gate electrode and the selection gate electrode with desired thickness and material by a design choice while obtaining the predictable gate electrode and the selection gate electrode characteristics.
Regarding claim 11, Kashima in view of Ryu teaches wherein the second channel structure includes a second ferroelectric layer (43) that surrounds the first portion of the second channel layer, and the first portion overlaps the second portion in the direction (Kashima, Fig. 22 and paragraph 96-97 and Ryu for the ferroelectric layer as discussed in claim 1).
Regarding claim 12, Kashima in view of Ryu teaches further comprising: a second blocking layer (42 blocking a contact between 41 and 43) positioned between the second ferroelectric layer and the selection gate electrode (Kashima, Fig. 23B and paragraph 71 and Ryu for the ferroelectric material), wherein the second blocking layer is positioned on a bottom surface of the second ferroelectric layer (Kashima, Fig. 23B, 42 positioned on a bottom surface of 43 and Ryu for the ferroelectric layer as discussed in claim 1).
Regarding claim 13, Kashima teaches wherein the first to third portions of the second channel layer include a same material (Fig. 16 and paragraph 119).
Regarding claim 14, referring to Figs. 4, 22, and 23B, Kashima teaches a semiconductor device comprising: a substrate (20) (paragraph 65); a stacked structure including a plurality of gate electrodes (23) stacked on the substrate and spaced apart from each other (paragraphs 67-68); a first channel structure (LP of MP) including (i) a first channel layer (31) extending through the stacked structure and extending along a direction (a z-direction), (ii) a first dielectric layer (32) positioned between the first channel layer and the stacked structure, and (iii) a channel recess extending into a portion of the first dielectric layer ((1) see the rejection of the claim under 35 U.S.C. 112(a) as discussed above and (2) the limitation “(iii) a channel recess extending into a portion of the first dielectric layer” is considered as a channel recess extending on an upper surface of the first dielectric layer and (3) Kashima in Fig. 23B shows a recessed region on an upper surface of 32 where 41’b is formed thereon) (see an annotated Fig. 23B above for “a channel recess” and paragraphs 70-74, 89-90, and 99); an insulating pattern (55) positioned on the stacked structure (paragraph 111); a selection gate electrode (24) positioned on the insulating pattern (paragraph 68); and a second channel structure (UP of MP) overlapping at least a portion of the first channel structure in the direction, and including a second channel layer (41) connected to the first channel structure through the selection gate electrode and the insulating pattern (paragraphs 68-71), and a second insulating layer (43) positioned between the second channel layer and the selection gate electrode (paragraphs 96-97), wherein the second channel layer includes: (a first portion a top portion of 41 through 24) extending through the selection gate electrode (Figs. 22 and 23B); a second portion (a middle portion of 41 including a top portion of 41’b through 55, wherein the top portion of 41’b is contacting a top surface of 31) extending through the insulating pattern and contacting an upper surface of the first channel layer (Figs. 22 and 23B); a third portion (a bottom portion of 41 including a bottom portion of 41’b between 32 and the middle portion of 41, and contacting a side surface of 31) positioned between the first insulating layer and the second portion and contacting a side surface of the first channel layer (Figs. 22 and 23B), and wherein the third portion fills the channel recess (41’b partially fills the channel recess) (see the annotated Fig. 23B above).
Kashima does not explicitly teach that the first dielectric layer (32) includes a first ferroelectric layer. Ryu teaches a semiconductor device (100) comprising: a channel structure (CH) including a channel layer (140) and a first dielectric layer including a first ferroelectric layer (145 including 144 formed of HfSiO) between the channel layer and a gate electrode (130) in order to provide the high-k dielectric material for reducing leakage current from the gate electrode (Figs. 4A-4C and paragraphs 39 and 49-50). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Kashima with that of Ryu in order to provide the high-k dielectric material for reducing leakage current from the gate electrode.
Regarding claim 15, Kashima in view of Ryu teaches wherein a width of the third portion in a radial direction from a center of the first channel structure is greater than a width of the first ferroelectric layer in the radial direction (Kashima, Fig. 23B, the bottom portion of 41’b in a radial direction is greater than a width of 32 and Ryu for the first ferroelectric layer).
Regarding claim 16, Kashima teaches wherein a thickness of the second portion in the direction (a thickness of the middle portion of 41 including the top portion of 41’b in the z-direction) is equal to a width of the third portion in the radial direction from the center of the first channel structure (a width of the bottom portion of 41’b in a y-direction) (Fig. 23B).
Regarding claim 17, Kashima in view of Ryu teaches wherein a first side portion of the first ferroelectric layer (a left-side portion of 32 shown in Fig. 23B) is in contact with the second channel layer, and a second side portion of the first ferroelectric layer (a right-side portion of 32 shown in Fig. 23B) is in contact with the insulating pattern (Kashima, Fig. 23B and Ryu for the ferroelectric material).
Regarding claim 18, Kashima teaches wherein a portion of the upper surface of the first channel layer (a left-side portion of an upper surface of 31) is in contact with the second channel layer, and a remaining portion of the upper surface of the first channel layer (a right-side portion of the upper surface of 31) is in contact with the insulating pattern (Fig. 23B).
Regarding claim 19, referring to Figs. 1, 4, 22, and 23B, Kashima teaches an electronic system comprising: a main substrate (20) (paragraph 65); a semiconductor device (1) on the main substrate (paragraphs 56 and 36); and a controller (2) electrically connected to the semiconductor device on the main substrate (paragraphs 36-45), wherein the semiconductor device includes: a peripheral circuit region (a region for 11-16); a cell region (10) including an input/output connection wire (input/output connections to and from 10 with 11-16) electrically connected to the peripheral circuit region (Fig. 1 and paragraph 37-38 and 65); wherein the cell region includes: a substrate (21) (paragraph 65); a stacked structure including a plurality of gate electrodes (23) stacked on the substrate and spaced apart from each other (paragraphs 67-68); a first channel structure (LP of MP) including (i) a first channel layer (31) extending through the stacked structure and extending along a direction (a z-direction), (ii) a first dielectric layer (32) positioned between the first channel layer and the stacked structure, and (iii) a channel recess extending into a portion of the first dielectric layer ((1) see the rejection of the claim under 35 U.S.C. 112(a) as discussed above and (2) the limitation “(iii) a channel recess extending into a portion of the first dielectric layer” is considered as a channel recess extending on an upper surface of the first dielectric layer and (3) Kashima in Fig. 23B shows a recessed region on an upper surface of 32 where 41’b is formed thereon) (see an annotated Fig. 23B above for “a channel recess” and paragraphs 70-74, 89-90, and 99); an insulating pattern (55) positioned on the stacked structure (paragraph 111); a selection gate electrode (24) positioned on the insulating pattern (paragraph 68); and a second channel structure (UP of MP) connected to the first channel structure through the selection gate electrode and the insulating pattern and including a second channel layer (41) extending along the direction (paragraphs 68-71), wherein the second channel layer includes: a first portion (a top portion of 41 through 24) extending through the selection gate electrode (Figs. 22 and 23B); a second portion (a middle portion of 41 including a top portion of 41’b through 55, wherein the top portion of 41’b is contacting a top surface of 31) extending through the insulating pattern and contacting an upper surface of the first channel layer (Figs. 22 and 23B); a third portion (a bottom portion of 41 including a bottom portion of 41’b protruding from a bottom surface of the middle portion of 41, and contacting an outer surface of 31) protruding from a lower surface of the second portion and contacting a side surface of the first channel layer (Figs. 22 and 23B), and wherein the third portion fills the channel recess (41’b partially fills the channel recess) (see the annotated Fig. 23B above).
Kashima does not explicitly teach that an input/output pad electrically connected to the input/out connection wire extending into the cell region and the first dielectric layer (32) includes a first ferroelectric layer. Ryu teaches a semiconductor device (100) comprising: a peripheral circuit region (30/PERI) and a cell region (20/CELL) on a main substrate (201), wherein an input/output pad (for example, 280) electrically connected to an input/out connection wire (a variety of vertical and horizontal connections (not shown) between 20/CELL with 30/PERI) extending into the cell region to provide the electrical connection between the cell region and the peripheral circuit region (Figs. 1 and 9 and paragraphs 26 and 101-105). Furthermore, Ryu teaches that the semiconductor device comprising: a channel structure (CH) including a channel layer (140) and a first dielectric layer including a first ferroelectric layer (145 including 144 formed of HfSiO) between the channel layer and a gate electrode (130) in order to provide the high-k dielectric material for reducing leakage current from the gate electrode (Figs. 4A-4C and paragraphs 39 and 49-50). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Kashima with that of Ryu in order to provide the electrical connection between the cell region and the peripheral circuit region and to provide the high-k dielectric material for reducing leakage current from the gate electrode.
Regarding claim 20, Kashima in view of Ryu teaches wherein the third portion is positioned on the first ferroelectric layer, and in a plan view, at least a portion of the third portion overlaps the second portion, and a remaining portion of the third portion does not overlap the second portion (Kashima, Fig. 23B and Ryu for the ferroelectric material).
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot in view of new grounds of rejections as set forth above in this Office Action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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