DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-12 recite the limitation " the conductive layer " in claim 7. There is insufficient antecedent basis for this limitation in the claim. It is unclear if this is referring to the plurality of conductive layers or one of the first, second, or third conductive layers.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 7-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 9107290).
Regarding claim 1, Chen discloses a power module (Fig. 1-8), comprising: an insulation layer (Fig. 4, 10/15), a plurality of conductive layers (Fig. 4, 12/13/16), a decoupling capacitor (Fig. 4, 11c), and a plurality of first components (Fig. 4, 14/11a), wherein the insulation layer comprises a plurality of sub-insulation layers (Fig. 4, 10/15) stacked in a thickness direction (Fig. 4, up and down) of the power module, and the sub-insulation layer is disposed between every two adjacent conductive layers (Fig. 4); the power module comprises a first region (Fig. 4, at 10), the sub-insulation layer located in the first region has a first accommodation cavity (Fig. 4, at the components), at least one first component of the plurality of first components is located in the first accommodation cavity (Fig. 4), the conductive layer adjacent to the sub-insulation layer at which the at least one first component is disposed is electrically connected to the at least one first component (Fig. 4, 13 connected to 11a), and at least some of the plurality of first components are stacked in the thickness direction of the power module (Fig. 4); and the insulation layer located in the first region has an auxiliary accommodation cavity (Fig. 4, at components), the decoupling capacitor is located in the auxiliary accommodation cavity (Fig. 4), a first pin (Fig. 4, left pin of 11c) of the decoupling capacitor is electrically connected to one layer of the plurality of conductive layers (Fig. 4, connected to 13), and a second pin (Fig. 4, right pin) of the decoupling capacitor is electrically connected to another layer of the plurality of conductive layers (Fig. 4, connected to 12).
The Examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP §2114. The recitation of “decoupling capacitor” does not distinguish the present invention over the prior art of Chen who teaches the structure as claimed.
Regarding claim 2, Chen further discloses that the insulation layer comprises a first side and a second side (Fig. 4, bottom of 10 and top of 15) that are disposed opposite to each other in the thickness direction of the power module (Fig. 4), and the plurality of conductive layers comprise a first conductive layer (Fig. 4, 13), a second conductive layer (Fig. 4, 16), and at least one third conductive layer (Fig. 4, 12); and the first conductive layer is located on the first side, the second conductive layer is located on the second side, and the third conductive layer is located between the first conductive layer and the second conductive layer (Fig. 4).
Regarding claim 3, Chen further discloses that that the plurality of conductive layers comprise the at least one third conductive layer comprises: there is one third conductive layer (Fig. 4, 12), the plurality of sub-insulation layers comprise a first sub-insulation layer (Fig. 4, 10) and a second sub-insulation layer (Fig. 4, 15), the first sub-insulation layer is located between the first conductive layer and the third conductive layer (Fig. 4), and the second sub-insulation layer is located between the second conductive layer and the third conductive layer (Fig. 4); the plurality of first components comprise a first transistor (Fig. 4, 11b) and a second transistor (Fig. 4, 17a), the first transistor is located at the first sub-insulation layer (Fig. 4), and the second transistor is located at the second sub-insulation layer (Fig. 4); and a first electrode and a control electrode of the first transistor are electrically connected to the first conductive layer (Fig. 4, bottom electrode of 11b), a second electrode of the first transistor is electrically connected to a first electrode of the second transistor through the third conductive layer (Fig. 4, thru 12), a control electrode of the second transistor is electrically connected to the third conductive layer (Fig. 4, bottom of 17a), and a second electrode of the second transistor is electrically connected to the second conductive layer (Fig. 4, top of 17a).
Regarding claim 4, Chen further discloses that that a first pin of the decoupling capacitor is electrically connected to one layer of the plurality of conductive layers (Fig. 3, to layer 13), and a second pin of the decoupling capacitor is electrically connected to another layer of the plurality of conductive layers (Fig. 4, layer 12) comprises: the first pin of the decoupling capacitor is electrically connected to the first electrode of the first transistor through the first conductive layer (Fig. 4, thru 13), and the second pin of the decoupling capacitor is electrically connected to the second electrode of the second transistor through the second conductive layer (Fig. 5, connected to top of 17a thru 12, 16, 50, and 150).
Regarding claim 7, Chen further discloses that the conductive layer comprises a plurality of sub-conductive layers stacked in the thickness direction of the power module; and two adjacent sub-conductive layers are in contact; or two adjacent sub-conductive layers are disposed at spacings (Fig. 4, 12 and 16 are spaced), the sub-insulation layer is disposed between the two adjacent sub-conductive layers (Fig. 4, 15 is between them), and the two adjacent sub-conductive layers are electrically connected through a conductive hole provided in the sub-insulation layer (Fig. 4, conductive vias under 160).
Regarding claim 8, Chen further discloses that a plurality of sub-conductive layers of a same conductive layer comprise a first sub-conductive layer and a second sub-conductive layer (Fig. 4, 32 and 13), and a thickness of the first sub-conductive layer is greater than a thickness of the second sub-conductive layer (Fig. 2, 32 is thicker than 13).
Regarding claim 9, Chen further discloses that a first sub-conductive layer of the first conductive layer is located on a side that is of a second sub-conductive layer of the first conductive layer and that faces away from the second side (Fig. 4, 32 is on far side of 13 from 12); and a first sub-conductive layer of the second conductive layer is located on a side that is of a second sub-conductive layer of the second conductive layer and that faces away from the first side (Fig. 4, 40 is on far side of 16 from 12).
Regarding claim 10, Chen further discloses that the power module further comprises a plurality of second components (Fig. 4, components in 15), the power module comprises a second region (Fig. 4, at 17a), the second region is located on at least one side of the first region (Fig. 4, top side), at least one second component of the plurality of the second components is located in the second region (Fig. 4, 17a), and the at least one second component is electrically connected to the at least one first component through the conductive layer (Fig. 4); and a sum of powers of all the plurality of first components is greater than a sum of powers of all the plurality of second components (Fig. 4, 1st region is considered to be all of the components in 10 and second region is just 17a).
Regarding claim 11, Chen further discloses that the power module further comprises a second accommodation cavity (Fig. 4, at 17a), the second accommodation cavity is located at a sub-insulation layer in the second region (Fig. 4), and the at least one second component is located in the second accommodation cavity (Fig. 4); or the at least one second component is located on a side that is of at least one of the first conductive layer and the second conductive layer and that faces away from the insulation layer; or the power module further comprises a second accommodation cavity, wherein the second accommodation cavity is located at the sub-insulation layer in the second region (Fig. 4), some of the plurality of second components are located in the second accommodation cavity (Fig. 4), and the others of the plurality of second components are located on a side that is of at least one of the first conductive layer and the second conductive layer and that faces away from the insulation layer (Fig. 4).
Regarding claim 12, Chen further discloses that respective first sub-conductive layers of the first conductive layer and the second conductive layer are all located in the first region (Fig. 4, when region is expanded to include them), and respective second sub-conductive layers of the first conductive layer and the second conductive layer are all located in the first region and the second region (Fig. 4, when region is expanded to include them); and a first sub-conductive layer and a second sub-conductive layer of the third conductive layer are located in the first region and the second region (Fig. 4, 12 and 103 is located there).
Regarding claim 13, Chen further discloses that the power module comprises a heat dissipation member (Fig. 4, 31), the heat dissipation member is disposed on a side that is of the first conductive layer and the second conductive layer and that faces away from the insulation layer (Fig. 4), and the heat dissipation member is located in the first region (Fig. 4, when included in the first region).
Regarding claim 14, Chen further discloses that the power module comprises a thermally conductive insulation layer (Fig. 4, 30), the thermally conductive insulation layer is disposed on a side that is of the heat dissipation member and that faces the insulation layer (Fig. 4), and the thermally conductive insulation layer is located in the first region (Fig. 4).
Regarding claim 15, Chen further discloses that the power module comprises a conductive pillar (Fig. 4, below 160), the sub-insulation layer has a third accommodation cavity (Fig. 4, at pillars below 160), the conductive pillar is located in the third accommodation cavity (Fig. 4), and two conductive layers adjacent to the sub-insulation layer at which the conductive pillar is disposed are electrically connected to the conductive pillar (Fig. 4).
Regarding claim 16, Chen discloses a power conversion device (Fig. 1-8), comprising a circuit board (Col 6, lines 1-17) and a plurality of power modules (Fig. 8, 1 and other 1), wherein the plurality of power modules are all disposed on the circuit board (Col 6, lines 1-17), and wherein each power module of the plurality of power modules comprises: a first region (Fig. 4, at 10), an insulation layer (Fig. 4, 10/15), a plurality of conductive layers (Fig. 4, 12/13/16), a decoupling capacitor (Fig. 4, 11c), and a plurality of first components (Fig. 4, 11 and 14), wherein the insulation layer comprises a plurality of sub- insulation layers stacked in a thickness direction of the power module (Fig. 4, 10/15 in thickness direction), and the sub-insulation layer is disposed between every two adjacent conductive layers (Fig. 4); the sub-insulation layer located in the first region has a first accommodation cavity (Fig. 4, at 11a), at least one first component of the plurality of first components is located in the first accommodation cavity (Fig. 4), the conductive layer adjacent to the sub-insulation layer at which the at least one first component is disposed is electrically connected to the at least one first component (Fig. 4, 13 connected to 11a), and at least some of the plurality of first components are stacked in the thickness direction of the power module (Fig. 4); and the insulation layer located in the first region has an auxiliary accommodation cavity (Fig. 4, at 11c), the decoupling capacitor is located in the auxiliary accommodation cavity (Fig. 4), a first pin of the decoupling capacitor is electrically connected to one layer of the plurality of conductive layers (Fig. 4, left pin to 13), and a second pin of the decoupling capacitor is electrically connected to another layer of the plurality of conductive layers (Fig. 4, right pin to 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 9107290).
Regarding claim 5, Chen fails to teach the claim limitations.
However, it would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to build the device so that the power module further comprises an insulation fastener, and the insulation fastener is located between the decoupling capacitor and a cavity wall of the auxiliary accommodation cavity, to better connect the capacitor to the insulating layer, in order to construct the devices using known designs in the art to meet user needs based on known design possibilities such as using an insulation fastener for better adhesion or not using one to save on cost.
Regarding claim 6, Chen further discloses that the power module further comprises a first connection portion (Fig. 4, 105 at bottom left of 11c) and a second connection portion (Fig. 4, 105 at top of 11c), the first connection portion is disposed at the conductive layer electrically connected to the first pin (Fig. 4), the first connection portion is electrically connected to the first pin (Fig. 4); and the second connection portion is disposed at the conductive layer electrically connected to the second pin (Fig. 4), the second connection portion is electrically connected to the second pin (Fig. 4).
However, Chen fails to teach that a material of the first connection portion is the same as a material of the first pin and a material of the second connection portion is the same as a material of the second pin.
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to make it so that a material of the first connection portion is the same as a material of the first pin and a material of the second connection portion is the same as a material of the second pin, so that you could save on cost of needing multiple materials and they could better bond, in order to construct the devices using known materials in the art to meet user needs based on known material properties and availability of those materials. The use of conventional materials/components to perform their known function is obvious. MPEP 2144.06.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 9107290) in view of Chen (US 20150303164 “Chen 164”).
Regarding claim 17, Chen discloses that a power conversion device comprises a circuit board (Col 6, lines 1-17) and a plurality of power modules (Fig. 8, 1 and 1), wherein the plurality of power modules are all disposed on the circuit board (Col 6, lines 1-17), and wherein each power module of the plurality of power modules comprises: a first region (Fig. 4, at 10), an insulation layer (Fig. 4, 10/15), a plurality of conductive layers (Fig. 4, 12/13/16), a decoupling capacitor (Fig. 4, 11c), and a plurality of first components (Fig. 4, 11 and 14), wherein the insulation layer comprises a plurality of sub- insulation layers stacked in a thickness direction of the power module (Fig. 4, 10/15 in thickness direction), and the sub-insulation layer is disposed between every two adjacent conductive layers (Fig. 4); the sub-insulation layer located in the first region has a first accommodation cavity (Fig. 4, at 11a), at least one first component of the plurality of first components is located in the first accommodation cavity (Fig. 4), the conductive layer adjacent to the sub-insulation layer at which the at least one first component is disposed is electrically connected to the at least one first component (Fig. 4, 13 connected to 11a), and at least some of the plurality of first components are stacked in the thickness direction of the power module (Fig. 4); and the insulation layer located in the first region has an auxiliary accommodation cavity (Fig. 4, at 11c), the decoupling capacitor is located in the auxiliary accommodation cavity (Fig. 4), a first pin of the decoupling capacitor is electrically connected to one layer of the plurality of conductive layers (Fig. 4, left pin to 13), and a second pin of the decoupling capacitor is electrically connected to another layer of the plurality of conductive layers (Fig. 4, right pin to 12).
However, Chen fails to teach a vehicle, comprising a housing and a power conversion device, wherein the power conversion device is located in the housing.
Chen 164 teaches a vehicle ([0002]), comprising a housing and a power conversion device ([0003]), wherein the power conversion device is located in the housing ([0003]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chen 164 to the invention of Chen, in order to connect the module to a next level component so it could be used as intended (Chen 164 [0002-0004]).
Regarding claim 18, Chen, in view of Chen 164, further teaches that the insulation layer comprises a first side and a second side (Fig. 4, bottom of 10 and top of 15) that are disposed opposite to each other in the thickness direction of the power module (Fig. 4), and the plurality of conductive layers comprise a first conductive layer (Fig. 4, 13), a second conductive layer (Fig. 4, 16), and at least one third conductive layer (Fig. 4, 12); and the first conductive layer is located on the first side, the second conductive layer is located on the second side, and the third conductive layer is located between the first conductive layer and the second conductive layer (Fig. 4).
Regarding claim 19, Chen, in view of Chen 164, further teaches that that the plurality of conductive layers comprise the at least one third conductive layer comprises: there is one third conductive layer (Fig. 4, 12), the plurality of sub-insulation layers comprise a first sub-insulation layer (Fig. 4, 10) and a second sub-insulation layer (Fig. 4, 15), the first sub-insulation layer is located between the first conductive layer and the third conductive layer (Fig. 4), and the second sub-insulation layer is located between the second conductive layer and the third conductive layer (Fig. 4); the plurality of first components comprise a first transistor (Fig. 4, 11b) and a second transistor (Fig. 4, 17a), the first transistor is located at the first sub-insulation layer (Fig. 4), and the second transistor is located at the second sub-insulation layer (Fig. 4); and a first electrode and a control electrode of the first transistor are electrically connected to the first conductive layer (Fig. 4, bottom electrode of 11b), a second electrode of the first transistor is electrically connected to a first electrode of the second transistor through the third conductive layer (Fig. 4, thru 12), a control electrode of the second transistor is electrically connected to the third conductive layer (Fig. 4, bottom of 17a), and a second electrode of the second transistor is electrically connected to the second conductive layer (Fig. 4, top of 17a).
Regarding claim 20, Chen, in view of Chen 164, further teaches that that a first pin of the decoupling capacitor is electrically connected to one layer of the plurality of conductive layers (Fig. 3, to layer 13), and a second pin of the decoupling capacitor is electrically connected to another layer of the plurality of conductive layers (Fig. 4, layer 12) comprises: the first pin of the decoupling capacitor is electrically connected to the first electrode of the first transistor through the first conductive layer (Fig. 4, thru 13), and the second pin of the decoupling capacitor is electrically connected to the second electrode of the second transistor through the second conductive layer (Fig. 5, connected to top of 17a thru 12, 16, 50, and 150).
Additional Relevant Prior Art:
YIU et al (US 2012/0194148) teaches relevant art in Fig. 1.
Fujioka et al (US 2022/0140706) teaches relevant art in Fig. 1-4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P MCFADDEN whose telephone number is (571)270-5649. The examiner can normally be reached M-Thur 8am-9pm PST.
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/MICHAEL P MCFADDEN/Primary Examiner, Art Unit 2847
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