DETAILED ACTION
This action is responsive to the following: the amended claims and arguments made in amendment filed on April 22, 2026.
Claims 1-20 are pending. Claims 1, 9, and 16 are Independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed on April 22, 2026 are entered. Claims 1-20 are pending. The amendments to claims overcome the objections set forth in the non-final rejection mailed on December 23, 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 10573373) in view of Satoh (US 20230179192 A1).
Regarding Independent Claim 1, Watanabe teaches an apparatus, comprising:
a plurality of inverter circuits (Fig. 7: 110A-113A; figure clearly shows inverting the clock signals) configured to receive a corresponding plurality of clock signals (Fig.7: R0-R3) and provide a plurality of inverted clock signals;
a clock pulse circuit (Fig. 7: 110A-113A; figures shows NAND gates receiving inverted and non-inverted clock signals) configured to receive the plurality of inverted clock signals and the plurality of clock signals, and provide a plurality of clock pulses based at least in part on the plurality of inverted clock signals and the plurality of clock signals, the plurality of clock pulses having different phases (col 2 lines 51-55 “the read clock signals R0 to R3 are four-phase clock signals having a period twice as long as that of the clock signals WCKt and WCKc and are different in phase from one another by 90 degrees.”);
However, Watanabe fails to a phase splitter circuit that is configured to split the clock pulses and outputs serializer clock signals to a serializer.
Satoh teaches a plurality of phase splitter circuits (Fig. 2: 220a, 220b) configured to receive the plurality of clock pulses (Fig. 2: Ref0, Ref90), split the plurality of clock pulses into serializer clock signals (Fig. 2: CK_Out0-3), and provide the serializer clock signals; and
a serializer circuit (Fig. 2: 206) configured to receive data (Fig. 2: 234) and receive the serializer clock signals (Fig. 2: CK_Out0-3), and further configured to provide serialized data (Fig. 2: DQ/DQS) based at least in part on the serializer clock signals and the data.
Taking internal clock signals and passing them through a phase splitter allows for the production of a complimentary clock signals with opposite phase. Such clock signals are useful for clocking a serializer as it reads data out of a memory array and outputs serialized data as clocks that aren’t very close to being completely out of phase can cause data read errors and produce excess current consumption by the serializer circuit.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teaches of Satoh to the teachings of Watanabe to produce an apparatus with a clock circuit which outputs signals to phase splitters.
Regarding Claim 2, Watanabe and Satoh teach the limitations of claim 1. Satoh further teaches an input clock buffer circuit (Fig. 2: 212) comprising a plurality of driver circuits and configured to receive the plurality of clock signals (Fig. 2: CK, CKB), stabilize the plurality of clock signals, and provide the plurality of clock signals to the plurality of inverter circuits.
Regarding Claim 3, Watanabe and Satoh teach the limitations of claim 1. Satoh further teaches wherein the input clock buffer circuit (Fig. 2: 212) receives the plurality of clock signals (Fig. 2: Ref0, Ref90) from a clock divider circuit (Fig. 2: 210).
Regarding Claim 4, Watanabe and Satoh teach the limitations of claim 1. Watanabe teaches wherein the clock pulse circuit comprises a plurality of not and (NAND) gates (Fig. 7: 110A-113A; figures shows NAND gates receiving inverted and non-inverted clock signals) configured to shorten the pulse widths of the plurality of clock signals and the plurality of inverted clock signals (Col 2 lines 51-55 states that the clock pulses are 90 degrees out of phase. Since the NAND gates in Fig. 7 have two signals 90 degrees out of phase there is only sufficient overlap between pulses to produces pulses of half the length).
Regarding Claim 5, Watanabe and Satoh teach the limitations of claim 4. Watanabe further teaches wherein the plurality of NAND gates (Fig. 7: 110A-113A; figures shows NAND gates receiving inverted and non-inverted clock signals) comprise a plurality of groups of NAND gates, and wherein each group of NAND gates comprise a same number of NAND gates.
Regarding Claim 6, Watanabe and Satoh teach the limitations of claim 1. Watanabe further teaches wherein the plurality of clock signals are each shifted in phase by a same amount relative to each other (col 2 lines 51-55 “the read clock signals R0 to R3 are four-phase clock signals having a period twice as long as that of the clock signals WCKt and WCKc and are different in phase from one another by 90 degrees.”).
Regarding Independent Claim 16, Watanabe teaches a method, comprising:
receiving a plurality of clock signals (Fig.7: R0-R3) and a plurality of inverted clock signals (Fig. 7: 110A-113A; figure clearly shows inverting the clock signals);
providing a plurality of clock pulses (Fig. 7: 110A-113A; figures shows NAND gates receiving inverted and non-inverted clock signals) based at least in part on the plurality of clock signals and the plurality of inverted clock signals, the plurality of clock pulses having different phases (col 2 lines 51-55 “the read clock signals R0 to R3 are four-phase clock signals having a period twice as long as that of the clock signals WCKt and WCKc and are different in phase from one another by 90 degrees.”);
However, Watanabe fails to teach splitting the clock pulse.
Satoh teaches splitting (Fig. 2: 220a, 220b) the plurality of clock pulses (Fig. 2: Ref0, Ref90) into serializer clock signals (Fig. 2: CK_Out0-3);
receiving data (Fig. 2: 234); and
providing serialized data (Fig. 2: DQ/DQS) based at least in part on the serializer clock signals (Fig. 2: CK_Out0-3) and the data (Fig. 2: 234 Data).
Taking internal clock signals and passing them through a phase splitter allows for the production of a complimentary clock signals with opposite phase. Such clock signals are useful for clocking a serializer as it reads data out of a memory array and outputs serialized data as clocks that aren’t very close to being completely out of phase can cause data read errors and produce excess current consumption by the serializer circuit.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teaches of Satoh to the teachings of Watanabe to produce a method of producing clock pulses from clock signals and inverted clock signals and then splitting them before using the split signals to clock a serializer.
Regarding Claim 17, Watanabe and Satoh teach the limitations of claim 16.
Watanabe further teaches wherein a pulse width of a clock pulse of the plurality of clock pulses is shorter than a pulse width of a clock signal of the plurality of clock signals (Col 2 lines 51-55 states that the clock pulses are 90 degrees out of phase. Since the NAND gates in Fig. 7 to and signals 90 degrees out of phase there is only sufficient overlap between pulses to produces pulses of half the length).
Regarding Claim 18, Watanabe and Satoh teach the limitations of claim 16. Satoh teaches stabilizing (Fig. 2: 208, 212) the plurality of clock pulses before the receiving the plurality of clock signals (Fig. 2: R0-R3) and the plurality of inverted clock signals (Fig. 7: 110A-113A; figure clearly shows inverting the clock signals).
Regarding Claim 19, Watanabe and Satoh teach the limitations of claim 16. Watanabe further teaches wherein the plurality of clock signals are each shifted in phase by a same amount relative to each other (col 2 lines 51-55 “the read clock signals R0 to R3 are four-phase clock signals having a period twice as long as that of the clock signals WCKt and WCKc and are different in phase from one another by 90 degrees.”).
Regarding Claim 20, Watanabe and Satoh teach the limitations of claim 16. Satoh further teaches selectively providing the serialized data (Fig. 2: DQ/DQS) based at least in part on the timing of the serializer clock signals (Fig. 2: CK_Out0-3).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 10573373) and Satoh (US 20230179192 A1) in view of Yoon (US 20240170085).
Regarding Claim 7, Watanabe and Satoh teach the limitations of claim 1.
However, Watanabe and Satoh fail to teach multiplexers.
Yoon teaches wherein the serializer circuit (Fig. 7: 411) comprises a plurality of multiplexers (Fig. 7: 414_1-414_4, 415_1-415_8) configured to selectively output the serialized data (Fig. 7: DOPU, DOPD) based at least in part on timing of the serializer clock signals (Fig. 7: CLK0, CLK90, CLK180, CLK270).
Multiplexer are a useful way of serializing data as they typically have one or more data input nodes and a select node, which allows the input data to be selectively output. Thus, they are useful for serializing data as they can be used to combine clock and data to produce a serialized data signal.
It would therefore have been obvious to one of ordinary skill in the art to apply the teachings of Yoon to the teachings of Satoh and Watanabe to produce an apparatus with a serializer circuit that comprises a plurality of
Claim 8, is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 10573373) and Satoh (US 20230179192 A1) in view of Lee et al (US 20190198075).
Regarding Claim 8, Watanabe and Satoh teach the limitations of claim 1.
However, Watanabe and Satoh fail to teach wherein at least one of the plurality of phase splitter circuits comprises a first line comprising two inverter circuits, and comprises a second line comprising three inverter circuits.
Lee teaches wherein at least one of the plurality of phase splitter circuits (Fig. 7: 710, 720, 730, 740) comprises a first line comprising two inverter circuits, and comprises a second line comprising three inverter circuits.
Using two inverters buffers the signal inputted to the phase splitter while an odd number of inverters will invert the signal. If the even numbered and odd numbered path are properly calibrated they will produce two complimentary signal 180 degrees out of phase. These signals can then be used to clock gates such as pull up and pull down gates downstream in predictable ways.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date to the claimed invention to apply the teachings of Lee to the teachings of Watanabe and Satoh to produce an apparatus with a phase splitter wherein the phase splitter consists of a one path with two inverter and a second path with three inverters.
Claims 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 10573373) in view of Satoh (US 20230179192 A1) and Yoon et al (US 20240170085).
Regarding Independent Claim 9, Watanabe teaches an apparatus, comprising:
a plurality of inverter circuits (Fig. 7: 110A-113A; figure clearly shows inverting the clock signals);
a first plurality of not and (NAND) logic gates (Fig. 7: 110A-113A; figures shows NAND gates receiving inverted and non-inverted clock signals), wherein corresponding outputs and inputs of the plurality of inverter circuits are coupled to corresponding inputs of the first plurality of NAND logic gates;
a second plurality of NAND logic gates (Fig. 7: 110B-113B; figures shows NAND gates receiving inputs from the first set of NAND gates in 110A-113A), wherein corresponding outputs of the first plurality of NAND logic gates are coupled to corresponding inputs of the second plurality of NAND logic gates;
However, Watanabe fails to a phase splitter circuits.
Satoh teaches a plurality of phase splitter circuits (Fig. 2: 220a, 220b)
Satoh teaches a serializer circuit (Fig. 2: 232)
However, Watanabe and Satoh fail to teach a serializer comprising a plurality of multiplexer circuits, wherein corresponding outputs of the phase splitter circuits are coupled to corresponding inputs of the plurality of multiplexer circuits.
Yoon teaches a serializer (Fig. 7: 411) comprising a plurality of multiplexer circuits (Fig. 7: 414_1-414_4, 415_1-415_8), wherein corresponding outputs of the phase splitter circuits (Fig. 5: 455) are coupled to corresponding inputs of the plurality of multiplexer circuits (Fig. 5: 456).
Taking internal clock signals and passing them through a phase splitter allows for the production of a complimentary clock signals with opposite phase. Such clock signals are useful for clocking a serializer as it reads data out of a memory array and outputs serialized data as clocks that aren’t very close to being completely out of phase can cause data read errors and produce excess current consumption by the serializer circuit.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teaches of Satoh to the teachings of Watanabe to produce an apparatus with a plurality of NAND gates which outputs signals to phase splitters.
Regarding Claim 10, Watanabe, Satoh and Yoon teach the limitations of claim 9.
Watanabe further teaches wherein there are twice as many of the first plurality of NAND logic gates as the second plurality of NAND logic gates.
Applicant discloses twice as many first NAND gates as second NAND gates but only teaches using the first NAND gates as inverters. Since the Fig. 3 and paragraph 33 of the specification of the disclosed invention show that the second input of NAND gates 335-a through 335-h are held at VDD. Watanabe discloses inverting each input to the logic gates 110A through 113A.
Regarding Claim 11, Watanabe, Satoh and Yoon teach the limitations of claim 9. Watanabe further teaches wherein an output of one NAND logic gate of the first plurality of NAND logic gates is coupled to an input of one NAND logic gate of the second plurality of NAND logic gates (Fig. 7: 110B-113B; figures shows NAND gates receiving inputs from the first set of NAND gates in 110A-113A).
Regarding Claim 12, Watanabe, Satoh and Yoon teach the limitations of claim 9. Satoh Further teaches wherein the serializer circuit (Fig. 2: 232) is coupled to an input/output (I/O) circuit (Fig. 2: 30) and coupled to a memory cell array (Fig. 1: 100).
Regarding Claim 13, Watanabe, Satoh and Yoon teach the limitations of claim 9. Yoon further teaches wherein at least one multiplexer (Fig. 10: 415_1) circuit of the plurality of multiplexer circuits comprises a NAND logic gate (Fig. 10: TR1, TR2, TR3, TR4), a not or (NOR) logic gate (Fig. 10: TR1, TR2, TR5, TR6), a p-channel transistor (Fig. 10: TR7), an n-channel transistor (Fig. 10: TR8), or a combination thereof.
Regarding Claim 14, Watanabe, Satoh and Yoon teach the limitations of claim 9. Satoh further teaches a plurality of driver circuits, wherein corresponding outputs of the plurality of driver circuits (Fig. 2: 212) are coupled to corresponding inputs of the plurality of inverter circuits (Fig. 2: 111, 121, 112, 122).
Regarding Claim 15, Watanabe, Satoh and Yoon teach the limitations of claim 9. Satoh further teaches wherein inputs to the plurality of driver circuits (Fig. 2: 212) are coupled to a clock divider circuit (Fig. 2: 210).
Response to Arguments
Applicant perfected the claim that the reference Satoh (US 20230412161 A1) did not qualify as prior art under the common ownership exception 102(b)(2)(C).
However, a new rejection under 35 U.S.C. 103 is now applied using the reference Satoh (US 20230179192 A1).
Conclusion
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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