DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant's election with traverse of invention II in the reply filed on 02/02/2026 is acknowledged. The traversal is on the ground(s) that the Restriction Requirement does not set forth an explanation related to any of the aforementioned categories. The “different keyword searches” rationale does not fall under any of the aforementioned categories. Moreover, the Restriction Requirement classifies both groups I and II under H04L7/0079 thus establishing that both groups I and II will be searched under the same classification. Accordingly, Applicant submits that the Examiner has not set forth the requirement to establish a serious search burden”.
This is not found persuasive because of the following:
Examiner would like to explain that the stated “different keyword searches” intends to indicate “employing different search queries” which shows the “A different field of search:” of MPEP §808.02.
Applicant has already cited MPEP §808.02 which states
(C) A different field of search: Where it is necessary to search for one of the inventions in a manner that is not likely to result in finding art pertinent to the other invention(s) (e.g., searching different classes/subclasses or electronic resources, or employing different search queries), a different field of search is shown, even though the two are classified together. The indicated different field of search must in fact be pertinent to the type of subject matter covered by the claims. Patents need not be cited to show different fields of search. (underlining was added by the Examiner).
Based on the above, even though Groups I and II are both classified in H04L/0079, employing different search queries shows a different field of search.
The requirement is still deemed proper and is therefore made FINAL.
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention. there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/03/2025.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 08/01/2025, 11/21/2025, 02/04/2026 have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Freebern (U.S. 2006/0291323).
With respect to claim 1, Freebern discloses:
generating a data bit (for example refer to the retrieving (generating) of input data (data in) out of a memory array which is not shown into the input paths of Fig. 4, [0015], lines 1-3 of [0021] “data is retrieved”, lines 3-8 of [0028] describe the “data in” also shown in Fig. 4, at least lines 3-5 [0029]. Regarding the claimed bit, refer to at least the data bit disclosed in the last sentence of [0022], the “data in” comprise at least a data bit); and subsequent to generating the data bit ([0031] Fig. 5 refer to steps 150 and 160 or 150 and 170, which take place after 110 is met (YES)(and after 100 takes place), at least lines 1-6 of [0032] the read command indicates that the data (out of the memory) is (already) onto the input data paths of Fig. 4, also refer to lines 1-3 of [0021]): monitoring for receipt of additional data (Fig. 5, step 110 monitoring for reception of an externally supplied clock signal corresponds to monitoring for received of additional data (additional information, presence of the external clock signal), [0031]-[0032]); in response to receipt of the additional data comprising clock signals (Fig. 5 step 110 YES and 150 (NO) or step 110 YES and 150 YES, the additional data comprises clock signals (the additional data comprise clock signals at different occasions, the clock signals (high clock and low clock) are not simultaneously present) refer to at least lines 6-12 of [0032], lines 1-5 of [0033], [0036]), determining a first type of communication based on the clock signals (e.g. synchronous type communication is determined in one of 160 (latched synchronous) or 170 (FIFO synchronous) also lines 3-6 of [0029]) and in response to an absence of the additional data (Fig. 5, step 110 NO output, [0032] no clock signal is present (high frequency clock or low frequency clock)), determining a second type of communication different from the first type of communication (asynchronous type communication 120), wherein the second type of communication comprises the data bit (the second type of communication data (asynchronous output of 50) comprises the data bit which is present in the “data in” (e.g. refer to Fig. 2, graph showing read data (including the data bit) and graph showing an asynchronous output (generated with a delay, shown by the arrow), refer to the description of [0022]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Freebern (U.S. 2006/0291323).
With respect to claim 2, Freebern discloses: in response to receipt of the
additional data comprising the clock signals (Fig. 5, in response to step 110 YES leading into 160 or 170), determining that a first device (e.g. memory array from which data in is received/read) is reading (or outputting) first data (read data out or output of the mux 56 of Fig. 5), herein the first data comprises the first type (synchronous type of 160 or 170) of communication.
Freebern does not expressly disclose (in the portions and Figures referenced above): transmitting to a second device.
Freebern however discloses: transmitting to a second device (last sentence of [0005] “During the read operation, the data path brings the data out of the memory array and onto the pads so that the data can be driver off the chip to another device via a bus or the like).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Freebern to perform determining that the memory array (first device) is transmitting first data (during the read operation of Fig. 5 which is met when 160 and 170 take place) to a second device (another device) because as explained by Freebern in the last sentence of [0005] during a read operation data out of a memory array is output and transmitted to another device.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Freebern (U.S. 2006/0291323) in view of Leonard (U.S. 7,230,497).
With respect to claim 5, Freebern discloses: in response to the clock signals transmitting a current state (of an input) (Fig. 5, 110 YES, and refer to mode selection logic 58 (which functions in response to inputs described in Fig. 4-5 and shown in Fig. 1, mode selection logic 22 with inputs shown), the presence of clock signals (at different occasions) in at least 110 supplied to the logic corresponds to transmitting a current state (of an input) indicating the presence of an external clock signal), transmitting data that comprises the first type of communication (Fig. 5 performing 160 or 170).
Freebern does not disclose: a current state of a pin over a network.
Implementing detection and use of an external clock signal, Leonard disclose: a current state of a pin over a network (column 5, at least lines 32-34, 65-66, Fig. 9 an external clock signal is received at an input pin, the clock signal transmitting a current state of a pin (input pin with an external clock signal present (current state)) over a network (wire/trace between the input pin and circuit where it is used).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fig. 4 of Freebern based on the teachings of Leonard, to include an input pin and network (trace) over which the clock signal indicator is supplied to 58, so that Fig. 4 of Freebern receives clock signals at an input pin as the clock signal presence indicator, the clock signals transmitting a current state of the pin over a network (trace) to logic 58 to perform the flow diagram of Fig. 5 using known and suitable components used to determine the presence of a clock.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Freebern (U.S. 2006/0291323) in view of Trimberger (U.S. 5,652,904).
With respect to claim 9, Freebern discloses: a multi-input input (device of Fig. 4,
[0029], refer to mode selection logic 58 and Fig. 5 (also refer to related Fig. 1 which shows inputs supplied to the mode selection logic [0021], although inputs to 58 are not shown in Fig. 4, they are disclosed in the description of Fig. 5 [0031] as pieces of information that are used to perform mode selection (they are input to the mode selection logic 58)); a frame generator circuit configured to generate a data bit (not shown in Fig. 5, but the Data In correspond to read data retrieved out of a memory array (as shown in Fig. 1 and discussed in Fig. 2) and refer to lines 1-3 of [0021] “data is retrieved”, lines 3-8 of [0028] describe the “data in” also shown in Fig. 4, at least lines 3-5 [0029]. Regarding the claimed bit, refer to at least the data bit disclosed in the last sentence of [0022], the “data in” comprise at least a data bit. The circuit which retrieves the “read data” out of the memory array according to the read command corresponds to the claimed frame generator circuit. Refer to lines 1-3 of [0021] also applicable to Fig. 4. Additionally refer to Figure 2 the read data from column, [0022] and [0023] describing different data path modes and); and an integrated circuit (chip disclosed in at least lines 6-8 as relating to the device of Fig. 1, also refer lines 1-6 of [0028] and the (memory) device (chip) of Fig. 4) configured to, subsequent to the frame generator circuit generating the data bit ([0031] Fig. 5 refer to steps 150 and 160 or 150 and 170, which take place after 110 is met (YES)(and after 100 takes place), at least lines 1-6 of [0032] the read command indicates that the data (out of the memory) is (already) onto the input data paths of Fig. 4, also refer to lines 1-3 of [0021]): monitor, at the multi-input input for receipt of additional data (Fig. 5, step 110 monitoring for reception of an externally supplied clock signal corresponds to monitoring for received of additional data (additional information, presence of the external clock signal), [0031]-[0032]); in response to receipt of the additional data comprising clock signals (Fig. 5 step 110 YES and 150 (NO) or step 110 YES and 150 YES, the additional data comprises clock signals (the additional data comprise clock signals at different occasions, the clock signals (high clock and low clock) are not simultaneously present) refer to at least lines 6-12 of [0032], lines 1-5 of [0033], [0036]), determine a first type of communication based on the clock signals (E.g. synchronous type communication is determined in one of 160 (latched synchronous) or 170 (FIFO synchronous) also lines 3-6 of [0029] based on the clock signals (high frequency or low frequency)) ; and in response to an absence of the additional data (Fig. 5, step 110 NO output, [0032] no clock signal is present (high frequency or low frequency clock signals)), determine a second type of communication (asynchronous type communication 120) different from the first type of communication, wherein the second type of communication comprises the data bit (the second type of communication data (asynchronous output of 50) comprises the data bit which is present in the “data in” (e.g. refer to Fig. 2, graph showing read data (including the data bit) and graph showing an asynchronous output (generated with a delay, shown by the arrow), refer to the description of [0022]).
Freebern does not disclose: a multi-pin interface; the multi-pin interface.
In the field of programmable logic devices, Trimberger discloses: a multi-pin interface (refer to at least column 1, lines 8-11, 14-35, refer to the listed well known programmable logic devices used to perform a logic function selected (programmed) by a user. “Once these devices have been programmed by the user, certain external pins serve as input pins, others pins serve as output pins…The device provides signals on the output pins in response to signals and combinations of signals placed on input pins as determined by the function which has been programmed into the device by the user.” At least the external pins serving as input pins correspond to a “multi-pin interface” as they provide an interface for signals to be input to the programmable logic device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement mode selection logic 58 of Freebern as a programmable logic device (PLD) (comprising a multi-pin interface as explained above) according to the teachings of Trimberger regarding programmable logic devices, to perform the mode selection (performed by 58) using a PLD (e.g. a PLA, FPGA, or EPLD) which is well known in the art programmable device optimized for speed, flexibility, complexity, or low cost (Trimberger, column 1, lines 8-35).
Allowable Subject Matter
Claims 3-4, 6-8, 10-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhou et al. (U.S. 10,880,116) entire document is relevant. Figure 1-5 disclose various embodiments of a multi-mode communication interface comprising a detection circuit. The detection circuit detects a communication format, and enables one of two receiver circuits based on the detected communication format.
Jones et al. (U.S. 2016/0037123) refer to at least the flowchart of Fig. 3.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA VLAHOS whose telephone number is (571)272-5507. The examiner can normally be reached M 8:00-4:00, TWRF 8:00-2:00.
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SOPHIA VLAHOS
Examiner
Art Unit 2633
/SOPHIA VLAHOS/Primary Examiner, Art Unit 2633 2/20/2026