DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
In regard to claim 1 the applicant argues that Xu et al. (US 2021/0384181 A1; hereinafter “Xu”) fails to teach the following limitations:
a plurality of interconnected structures configured to electrically respectively connect the light emitting mesas, wherein the interconnected structures comprise one or more top interconnected structures configured to electrically connect to a top of each one of the two or more light emitting mesas and be bonded with the IC backplane, and one or more bottom interconnected structures each configured to electrically connect to a bottom of one of the two or more light emitting mesas and be bonded with the IC backplane, the interconnected structures being formed around the two or more light emitting mesas, one of the bottom interconnected structures connected to one light emitting mesa, and one of the top interconnected structures connected to each one of the two or more light emitting mesas;
wherein a top of each of the plurality of interconnected structures is equal to or higher than a top of a top-most light emitting mesa.
The examiner respectfully disagrees. The Applicant asserts the following:
Xu does not disclose these disparate elements as a unified "plurality of interconnected structures."
Xu, does not disclose or suggest one or more bottom interconnected structures each configured to electrically connect to a bottom of one of the two or more light emitting mesas and be bonded with the IC backplane.
In regard to assertion (a), Applicant argues each of these elements mapped to serve as the plurality of interconnected structures serves a distinct function. Examiner notes that while the functions of the elements may differ this does not disqualify the elements as an interconnect structure. Further, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ 2d 1647 (1987). So as the elements are connected and facilitate a current path within the device, they combined qualify as an interconnect structure. Also the examiner notes that applicant states “Reflective cup parts for light extraction, not electrical interconnection”, this is incorrect as Xu explicitly states “when the top electrode (layer) 140/440 electrically connect with each of the LED structures (e.g. the LED structures including the light emitting layers 112/412, 130/430 and 136/436) and optionally the top electrodes 142 and 144, the reflective cup may perform as a common P-electrode or N-electrode of the single pixel tri-color LED device” (paragraph 402).
In regard to assertion (b), Applicant asserts neither the contact pad 152 nor any of the disparate elements 122, 124, 126 is configured to electrically connect to a bottom of the light emitting mesa and being bonded with the IC backplane. The bottom of the green LED light emitting layer 130 which functions as the light emitting mesa to the circuitry in substrate 104 which functions as the integrated circuit (IC) backplane. The bottom of the light emitting layer 130 which is conductive layer 128 is shown connected to combined section 122, 124 and 126 and P-electrode contact components 122 and 124 are connected to a driver circuit 106 (paragraphs 200 and 202). Further as stated in Xu the P-electrode contact pad 152 is also connected to some P-electrode contact components (not shown in FIGS. 1A and 1B), similar to 122 and 124, within the planarized insulation layers 154 and 158, and within the transparent bonding layers 156 and 160. Those P-electrode contact components are connected to a driver circuit 106 (paragraph 211). As the term “bonded” refers to the way the layers were secured to one another, the method of forming a device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. Therefore, as the combined section 122, 124, 126 and pad 152 are connected to both the bottom of the light emitting layer and the circuitry in substrate 104 the claim limitation is met.
In regard to the amended limitation of claim 1, applicants arguments have been considered, and a new rejection in view of Chae (US 2022/0005792 A1) has been made.
Examiner acknowledges the title of the invention has been changed and is clearly indicative of the invention to which the claims are directed. Therefore the specification objection has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-5, 7-16, and 23-27 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (US 2021/0384181 A1; hereinafter “Xu”), and further in view of Chae (US 2022/0005792 A1).
In regard to claim 1, Xu teaches a micro LED display panel (a display panel with integrated micro-lens array) (paragraph 24), comprising:
a micro LED array comprising a plurality of micro LEDs (the micro-lens array contains micro tri-color LED structure 100) (Fig. 1B and paragraphs 184 and 377), wherein each one of the plurality of micro LEDs comprises two or more light emitting mesas which are disposed in a vertical direction from top to bottom (the LED light emitting layers 112, 130, and 136, are formed in a stacked structure) (Fig. 1B and paragraph 188);
an integrated circuit (IC) backplane (circuitry in substrate 104 includes contacts to each individual driver circuit 106 and also a ground contact) formed at a back surface of the micro LED array and configured to control the plurality of micro LEDs (the driver circuits 106 are thin-film transistor pixel drivers or silicon CMOS pixel drivers) (Fig. 1B and paragraph 185); and
a plurality of interconnected structures (combined sections 116, 118, 120, 122, 124, 126, top electrodes 140, 144, reflective cup parts 146,148, contact pad 152 and the circuitry connecting the driver circuits 106) configured to electrically respectively connect the light emitting mesas (Fig. 1B and paragraphs 186-187, and 402), wherein the interconnected structures comprise one or more top interconnected structures (the reflective cup parts 146 and 148) configured to electrically connect to a top of each one of the two or more light emitting mesas and be bonded with the IC backplane (the reflective cup may perform as a common P-electrode or N-electrode for the single pixel tri-color LED device with the adoption of the one or more top electrodes) (Fig. 1B and paragraph 402), and one or more bottom interconnected structures (combined sections 122, 124, 126, contact pad 152) each configured to electrically connect to a bottom of one of the two or more light emitting mesas and be bonded with the IC backplane (the combined sections connect LED light emitting layer130 to the driver circuits 106 as shown in Fig. 1B) (Fig. 1B and paragraphs 211), the interconnected structures being formed around the two or more light emitting mesas (the combined sections and reflective cup parts 146 and 148 are shown surrounding the LED light emitting layers 112, 130, and 136 in Fig. 1B), one of the bottom interconnected structures connected to one light emitting mesa (combined sections 122, 124 and 126 are connected to the bottom to the to the LED light emitting layer130 as shown in Fig. 1B), and one of the top interconnected structures connected to each one of the two or more light emitting mesas (the combined section 116, 118, and 120 are shown connected to the LED light emitting layers 112, 130 in Fig. 1B).
However, Xu fails to teach wherein a top of each of the plurality of interconnected structures is equal to or higher than a top of a top-most light emitting mesa.
Chae teaches a micro LED display panel (a display panel 1000) (Fig. 2 and paragraph 164), wherein a top of each of a plurality of interconnected structures (pillars 73A-73D) is equal to or higher than a top of a top-most light emitting mesa (the pillars 73a, 73b, 73c, and 73d are shown above the top-most light emitting mesa first LED stack 23) (Fig. 4A and paragraph 63).
It would have been obvious to one skilled in the art to combine the teachings of Chae with the teachings of Xu to have the top of each of the plurality of interconnected structures is equal to or higher than a top of a top-most light emitting mesa since this allows for reduction in light emitting areas of the LED stacks to be alleviated and improve light extraction efficiency as taught by Chae (paragraph 169).
In regard to claim 2, Xu teaches wherein a diameter of a top surface of each one of the light emitting mesas is smaller than a diameter of a bottom surface of the light emitting mesa (the LED structures of different colors have a trapezoidal shape as shown in Fig. 1B) (Fig. 1B and paragraph 241).
In regard to claim 3, Xu teaches wherein the micro LED further comprises a bottom bonding layer (metal bonding layer 108) provided between a bottom of a bottom-most one of the light emitting mesas and the IC backplane (Fig. 1B and paragraph 242).
In regard to claim 4, Xu teaches wherein a material of the bottom bonding layer is metal (the metal bonding layer 108 is formed of metal) (paragraph 242).
In regard to claim 5, Xu teaches wherein the material of the bottom bonding layer comprises at least one of Al, Au, Rh, Ag, Cr, Ti, Pt, Sn, Cu, AuSn, or TiW (the metal bonding layer 108 can include Au) (paragraph 193).
In regard to claim 7, Xu teaches herein the micro LED further comprises a conductive layer network structure (conductive layers 110, 114, 128, 132, 134, and 138) configured to connect the two or more light emitting mesas to the plurality of interconnected structures (Fig. 1B and paragraphs 194, 203, 211 and 220).
In regard to claim 8, Xu teaches wherein the conductive layer network structure comprises a top conductive layer formed on a top surface of each of the light emitting mesas and configured to connect the light emitting mesa with the top interconnected structure (conductive layers 114, 132, and 138 are shown on top of the LED light emitting layers 112, 130, and 136 and connect to the reflective cup parts 146 and 148 in Fig. 1B), and a bottom conductive layer (metal bonding layer 108, the conductive layer 128 and the conductive layer 134) formed at a bottom surface of each of the light emitting mesas and configured to connect the light emitting mesa with the bottom interconnected structure (the metal bonding layer 108, the conductive layer 128 and the conductive layer 134 all connect to their associated bottom interconnect structures as shown in Fig. 1B).
In regard to claim 9, Xu teaches wherein the top conductive layer is extended to connect the light emitting mesa with the top interconnected structure (the conductive layers 114, 132, and 138 are shown extending electrically connected to the reflective cup parts 146 and 148 in Fig. 1B).
In regard to claim 11, Xu teaches the micro LED further comprises an interconnected layer (top electrode 142) (Fig. 1B and paragraph 185), wherein a first end of the interconnected layer is formed on an edge of the top conductive layer and a second end of the interconnected layer is connected to the top interconnect structure (as shown in Fig. 1B the top electrode 142 is shown contacting the edge of top electrode 140 and the reflective cup parts 146).
In regard to claim 12, Xu teaches wherein the conductive layer network structure is transparent (the conductive layer 110 and the conductive transparent layer 114 are transparent) (paragraph 198).
In regard to claim 13, Xu teaches wherein a material of the conductive layer network structure is one of Indium Tin Oxide (ITO), Fluorine-doped Tin Oxide (FTO), or Aluminum-doped Zinc Oxide (AZO) (the conductive layer 114 is a conductive transparent layer 114, such as an ITO layer) (paragraph 194).
In regard to claim 14, Xu teaches wherein the interconnected structures are made of conductive metal (the combined section 116, 118, and 120, are made of materials such as graphene, ITO, Aluminum-Doped Zinc Oxide (AZO) (paragraph 186).
In regard to claim 15, Xu teaches wherein the interconnected structures are through-vias (via or through hole is formed within the planarized insulation layer 154 to accommodate the P-electrode contact components 122 and 124 for the green LED structure) (paragraph 200).
In regard to claim 16, Xu teaches the micro LED further comprises a dielectric material filled between the light emitting mesas and around the interconnected structures (planarized layers such as 154, 168, 162 and bonding layer such 156 and 160 are formed of dielectric materials and around the LED light emitting layers 112, 130, and 136 and combined sections 116, 118, 120, 122, 124, 126 as shown in Fig. 1B) (Fig. 1B and paragraph 199).
In regard to claim 23, Xu teaches wherein the IC backplane comprises an array of pad groups corresponding to the micro LED array (as shown in Fig. 1B river circuits 106 have associated pad groups), one of the pad groups corresponding to one micro LED, the two or more light emitting mesas comprise a first light emitting mesa, a second light emitting mesa and a third light emitting mesa which are disposed in the vertical direction from top to bottom (the pad groups of the river circuits 106 are shown connecting to the stacked the LED light emitting layers 112, 130, and 136 in the he tri-color LED device 100 in Fig. 1B), wherein the pad group comprises:
a first pad connected to the bottom bonding layer (the pad in the driver circuit 106 is shown connected to the metal bonding layer 108 in Fig. 1B);
a second pad connected to a first one of the bottom interconnected structures connected with a bottom of the first light emitting mesa (the pad in the driver circuit 106 is shown connected to the connection structure 122 in Fig. 1B); and
a third pad connected to a second one of the bottom interconnected structures connected with a bottom of the second light emitting mesa (the pad in the driver circuit 106 is connected to the connected to the conductive transparent layer 134 through the P-electrode contact pad 152) (paragraph 211).
In regard to claim 24, Xu teaches wherein the first light emitting mesa emits blue light ; the second light emitting mesa emits green light; and the third light emitting mesa emits red light (the red LED light emitting layer 112, the green LED light emitting layer 130 and the blue LED light emitting layer 136) (Fig. 1B and paragraph 223).
In regard to claim 25, Xu teaches wherein a height of the micro LED is from 1 µm to 10 µm (the he vertical height of the multi-color LED device 100 is 1 micron to 500 microns therefore, there exist a micro led range of 1 micrometers to 10 micrometers) (paragraph 242).
In regard to claim 26, Xu teaches wherein a height of one of the light emitting mesas is from 0.3 µm to 3.5 µm (the thickness of the blue LED light emitting layer is about 0.1 micron to about 5 microns) (paragraph 215).
In regard to claim 27, Xu teaches wherein a bottom most light emitting mesa of the two or more light emitting mesas emits red light (the red LED light emitting layer 112 is the bottom layer) (Fig. 1B and paragraph 223).
Claims 6 and 17-22 are rejected under 35 U.S.C. 103 as being unpatentable over Xu as taught in Fig. 1B in view of Chae as applied to claim 3 or 16 above, in view of Xu as taught in Fig. 4A.
In regard to claim 6, Xu as described in Fig. 1B and its associated text in view of Chae doesn’t explicitly teach, wherein a diameter of a top surface of the bottom bonding layer is equal to a diameter of a bottom surface of the bottom-most light emitting mesa.
Xu as described in Fig. 4A teaches wherein a diameter of a top surface of the bottom bonding layer is equal to a diameter of a bottom surface of the bottom-most light emitting mesa (the top surface of the metal bonding layer 408 has the same diameter as the bottom surface of the red LED light emitting layer 412 due to pyramid shape formed) (Fig. 4A, Fig. 4D and paragraph 241).
It would be obvious to one skilled in the art to combine the teachings of Xu shown in Fig. 1B in view of Chae with Xu as taught in Fig. 4A since a pyramid like structure can improve the electronic connections between the individual LED structures and to the electrodes, and simplify the fabrication process as taught by Xu (paragraph 241).
In regard to claim 17, Xu as described in Fig. 1B in view of Chae doesn’t explicitly teach a top dielectric layer continuously formed on a top surface of the micro LED array.
Xu as described in Fig. 4A teaches a top dielectric layer (planarized layer 476) continuously formed on a top surface of the micro LED array (Fig. 4D and paragraph 335).
It would’ve been obvious to one skilled in the art the time to combine the teachings of Xu as taught in Fig. 1B in view of Chae with Xu as taught in Fig. 4B to have a top dielectric layer continuously formed on a top surface of the micro LED array since this allows light to be emitted from the device while also protecting from unwanted shorts as taught by Xu (paragraph 335).
In regard to claim 18, Xu as described in Figs. 1B and 4A in view of Chae teaches wherein the top dielectric layer is transparent (the planarized layer, such as 476, is transparent to the light emitted from the micro LED) (Fig. 4D and paragraph 335).
In regard to claim 19, Xu as described in Figs. 1B and 4A in view of Chae teaches wherein material of the top dielectric layer is SiO2, SiN, SiON, or Al2O3 (the solid inorganic materials of the planarized layer 476 include SiO2) (paragraph 335).
In regard to claim 20, Xu as described in Figs. 1B and 4A in view of Chae teaches a plurality of micro lenses (a micro-lens 602) provided on the top dielectric layer, each of the micro lenses covering a pixel display area of one of the micro LEDs (the single pixel tri-color LED device 600 has similar structures as any one of the single pixel tri-color LED devices shown in FIGS. 1-5 with the addition of a micro-lens 602) (Fig. 6A and paragraph 365).
In regard to claim 21, Xu as described in Figs. 1B and 4A teaches wherein a diameter of a bottom surface of the micro lens is greater than a largest diameter of top surfaces of the two or more light emitting mesas (as shown in Fig. 6A the micro-lens 602 is shown with a bottom surface wider than a top surface than the LED light emitting layers 112, 130, and 136) (Fig. 6A).
In regard to claim 22, Xu as described in Figs. 1B and 4A teaches wherein a height of the micro lens is equal to or less than 10 µm. (he height of the micro-lens 602 is not more than 2 micrometers) (paragraph 375).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Chae as applied to claim 9 above, in view of Xu et al. (US 2021/0305220 A1; hereinafter “Xu220”).
In regard to claim 10, Xu in view of Chae doesn’t explicitly teach wherein the top conductive layer is continuously formed between adjacent micro LEDs.
Xu220, teaches a micro LED array comprising a plurality of micro LEDs (a tri-color LED device 100) (Fig. 1A and paragraph 51), wherein a top conductive layer is continuously formed between adjacent micro LEDs (a transparent conductive layer 05 is shown continuously formed between the micro LED structures 01, 02 and 03 in Fig. 1A) (Fig. 1A and paragraphs 51 and 93).
It would’ve been obvious to one skilled in the art to combine the teachings of Xu in view of Chae with the teachings of Xu220 to have the top conductive layer continuously formed between adjacent micro LEDs since this layout allows the manufacture of a device at reduced cost by reducing the intermediate steps and materials as taught by Xu (paragraph 95).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Chae as applied to claim 1 above, in view of Wang et al. (CN114093905A; hereinafter “Wang”).
In regard to claim 28, Xu in view of Chae doesn’t explicitly teach wherein a top most light emitting mesa emits green light.
Wang teaches a micro LED array comprising a plurality of micro LEDs (a stacked Micro LED full-color display) (Fig. 1 and paragraph 47), wherein a top most light emitting mesa emits green light (the plurality of pixel light-emitting units are any combination of red light-emitting units, blue light emitting where unit 5 is a green light-emitting unit) (Fig. 3 and paragraph 49).
It would’ve been obvious to one skilled in the art to combine the teachings of Xu in view of Chae with Wang to have a top most light emitting mesa emits green light since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Li et al. (US2020/0403026A1).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
