Prosecution Insights
Last updated: July 17, 2026
Application No. 18/653,909

MICRO LED DISPLAY PANEL

Non-Final OA §102§103
Filed
May 02, 2024
Priority
May 05, 2023 — CN PCT/CN2023/092170
Examiner
PUNCHBEDDELL, SEYON ALI-SIMAH
Art Unit
Tech Center
Assignee
Jade Bird Display (shanghai) Limited
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
1y 3m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
61 granted / 79 resolved
+17.2% vs TC avg
Moderate +6% lift
Without
With
+6.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
31 currently pending
Career history
110
Total Applications
across all art units

Statute-Specific Performance

§103
91.6%
+51.6% vs TC avg
§102
3.9%
-36.1% vs TC avg
§112
3.9%
-36.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 79 resolved cases

Office Action

§102 §103
DETAILED ACTION Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 1-5, 7-16, and 23-27 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Xu et al. (US 2021/0384181 A1; hereinafter “Xu”). In regard to claim 1, Xu teaches a micro LED display panel (a display panel with integrated micro-lens array) (paragraph 24), comprising: a micro LED array comprising a plurality of micro LEDs (the micro-lens array contains micro tri-color LED structure 100) (Fig. 1B and paragraphs 184 and 377), wherein each one of the plurality of micro LEDs comprises two or more light emitting mesas which are disposed in a vertical direction from top to bottom (the LED light emitting layers 112, 130, and 136, are formed in a stacked structure) (Fig. 1B and paragraph 188); an integrated circuit (IC) backplane (circuitry in substrate 104 includes contacts to each individual driver circuit 106 and also a ground contact) formed at a back surface of the micro LED array and configured to control the plurality of micro LEDs (the driver circuits 106 are thin-film transistor pixel drivers or silicon CMOS pixel drivers) (Fig. 1B and paragraph 185); and a plurality of interconnected structures (combined sections 116, 118, 120, 122, 124, 126, top electrodes 140, 144, reflective cup parts 146,148, contact pad 152 and the circuitry connecting the driver circuits 106) configured to electrically respectively connect the light emitting mesas (Fig. 1B and paragraphs 186-187, and 402), wherein the interconnected structures comprise one or more top interconnected structures (the reflective cup parts 146 and 148) configured to electrically connect to a top of each one of the two or more light emitting mesas and be bonded with the IC backplane (the reflective cup may perform as a common P-electrode or N-electrode for the single pixel tri-color LED device with the adoption of the one or more top electrodes) (Fig. 1B and paragraph 402), and one or more bottom interconnected structures (combined sections 122, 124, 126, contact pad 152) each configured to electrically connect to a bottom of one of the two or more light emitting mesas and be bonded with the IC backplane (the combined sections connect LED light emitting layer130 to the driver circuits 106 as shown in Fig. 1B) (Fig. 1B and paragraphs 211), the interconnected structures being formed around the two or more light emitting mesas (the combined sections and reflective cup parts 146 and 148 are shown surrounding the LED light emitting layers 112, 130, and 136 in Fig. 1B), one of the bottom interconnected structures connected to one light emitting mesa (combined sections 122, 124 and 126 are connected to the bottom to the to the LED light emitting layer130 as shown in Fig. 1B), and one of the top interconnected structures connected to each one of the two or more light emitting mesas (the combined section 116, 118, and 120 are shown connected to the LED light emitting layers 112, 130 in Fig. 1B); wherein a top of the plurality of interconnected structures is equal to or higher than a top of a top-most light emitting mesa (the top of the combined section 116, and 120 are shown higher than the LED light emitting layers 112, 130 in Fig. 1B). In regard to claim 2, Xu teaches wherein a diameter of a top surface of each one of the light emitting mesas is smaller than a diameter of a bottom surface of the light emitting mesa (the LED structures of different colors have a trapezoidal shape as shown in Fig. 1B) (Fig. 1B and paragraph 241). In regard to claim 3, Xu teaches wherein the micro LED further comprises a bottom bonding layer (metal bonding layer 108) provided between a bottom of a bottom-most one of the light emitting mesas and the IC backplane (Fig. 1B and paragraph 242). In regard to claim 4, Xu teaches wherein a material of the bottom bonding layer is metal (the metal bonding layer 108 is formed of metal) (paragraph 242). In regard to claim 5, Xu teaches wherein the material of the bottom bonding layer comprises at least one of Al, Au, Rh, Ag, Cr, Ti, Pt, Sn, Cu, AuSn, or TiW (the metal bonding layer 108 can include Au) (paragraph 193). In regard to claim 7, Xu teaches herein the micro LED further comprises a conductive layer network structure (conductive layers 110, 114, 128, 132, 134, and 138) configured to connect the two or more light emitting mesas to the plurality of interconnected structures (Fig. 1B and paragraphs 194, 203, 211 and 220). In regard to claim 8, Xu teaches wherein the conductive layer network structure comprises a top conductive layer formed on a top surface of each of the light emitting mesas and configured to connect the light emitting mesa with the top interconnected structure (conductive layers 114, 132, and 138 are shown on top of the LED light emitting layers 112, 130, and 136 and connect to the reflective cup parts 146 and 148 in Fig. 1B), and a bottom conductive layer (metal bonding layer 108, the conductive layer 128 and the conductive layer 134) formed at a bottom surface of each of the light emitting mesas and configured to connect the light emitting mesa with the bottom interconnected structure (the metal bonding layer 108, the conductive layer 128 and the conductive layer 134 all connect to their associated bottom interconnect structures as shown in Fig. 1B). In regard to claim 9, Xu teaches wherein the top conductive layer is extended to connect the light emitting mesa with the top interconnected structure (the conductive layers 114, 132, and 138 are shown extending electrically connected to the reflective cup parts 146 and 148 in Fig. 1B). In regard to claim 11, Xu teaches the micro LED further comprises an interconnected layer (top electrode 142) (Fig. 1B and paragraph 185), wherein a first end of the interconnected layer is formed on an edge of the top conductive layer and a second end of the interconnected layer is connected to the top interconnect structure (as shown in Fig. 1B the top electrode 142 is shown contacting the edge of top electrode 140 and the reflective cup parts 146). In regard to claim 12, Xu teaches wherein the conductive layer network structure is transparent (the conductive layer 110 and the conductive transparent layer 114 are transparent) (paragraph 198). In regard to claim 13, Xu teaches wherein a material of the conductive layer network structure is one of Indium Tin Oxide (ITO), Fluorine-doped Tin Oxide (FTO), or Aluminum-doped Zinc Oxide (AZO) (the conductive layer 114 is a conductive transparent layer 114, such as an ITO layer) (paragraph 194). In regard to claim 14, Xu teaches wherein the interconnected structures are made of conductive metal (the combined section 116, 118, and 120, are made of materials such as graphene, ITO, Aluminum-Doped Zinc Oxide (AZO) (paragraph 186). In regard to claim 15, Xu teaches wherein the interconnected structures are through-vias (via or through hole is formed within the planarized insulation layer 154 to accommodate the P-electrode contact components 122 and 124 for the green LED structure) (paragraph 200). In regard to claim 16, Xu teaches the micro LED further comprises a dielectric material filled between the light emitting mesas and around the interconnected structures (planarized layers such as 154, 168, 162 and bonding layer such 156 and 160 are formed of dielectric materials and around the LED light emitting layers 112, 130, and 136 and combined sections 116, 118, 120, 122, 124, 126 as shown in Fig. 1B) (Fig. 1B and paragraph 199). In regard to claim 23, Xu teaches wherein the IC backplane comprises an array of pad groups corresponding to the micro LED array (as shown in Fig. 1B river circuits 106 have associated pad groups), one of the pad groups corresponding to one micro LED, the two or more light emitting mesas comprise a first light emitting mesa, a second light emitting mesa and a third light emitting mesa which are disposed in the vertical direction from top to bottom (the pad groups of the river circuits 106 are shown connecting to the stacked the LED light emitting layers 112, 130, and 136 in the he tri-color LED device 100 in Fig. 1B), wherein the pad group comprises: a first pad connected to the bottom bonding layer (the pad in the driver circuit 106 is shown connected to the metal bonding layer 108 in Fig. 1B); a second pad connected to a first one of the bottom interconnected structures connected with a bottom of the first light emitting mesa (the pad in the driver circuit 106 is shown connected to the connection structure 122 in Fig. 1B); and a third pad connected to a second one of the bottom interconnected structures connected with a bottom of the second light emitting mesa (the pad in the driver circuit 106 is connected to the connected to the conductive transparent layer 134 through the P-electrode contact pad 152) (paragraph 211). In regard to claim 24, Xu teaches wherein the first light emitting mesa emits blue light ; the second light emitting mesa emits green light; and the third light emitting mesa emits red light (the red LED light emitting layer 112, the green LED light emitting layer 130 and the blue LED light emitting layer 136) (Fig. 1B and paragraph 223). In regard to claim 25, Xu teaches wherein a height of the micro LED is from 1 µm to 10 µm (the he vertical height of the multi-color LED device 100 is 1 micron to 500 microns therefore, there exist a micro led range of 1 micrometers to 10 micrometers) (paragraph 242). In regard to claim 26, Xu teaches wherein a height of one of the light emitting mesas is from 0.3 µm to 3.5 µm (the thickness of the blue LED light emitting layer is about 0.1 micron to about 5 microns) (paragraph 215). In regard to claim 27, Xu teaches wherein a bottom most light emitting mesa of the two or more light emitting mesas emits red light (the red LED light emitting layer 112 is the bottom layer) (Fig. 1B and paragraph 223). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 6 and 17-22 are rejected under 35 U.S.C. 103 as being unpatentable over Xu as taught in Fig. 1B as applied to claim 3 or 16 above, in view of Xu as taught in Fig. 4A. In regard to claim 6, Xu as described in Fig. 1B and its associated text doesn’t explicitly teach, wherein a diameter of a top surface of the bottom bonding layer is equal to a diameter of a bottom surface of the bottom-most light emitting mesa. Xu as described in Fig. 4A teaches wherein a diameter of a top surface of the bottom bonding layer is equal to a diameter of a bottom surface of the bottom-most light emitting mesa (the top surface of the metal bonding layer 408 has the same diameter as the bottom surface of the red LED light emitting layer 412 due to pyramid shape formed) (Fig. 4A, Fig. 4D and paragraph 241). It would be obvious to one skilled in the art to combine the teachings of Xu shown in Fig. 1B with Xu as taught in Fig. 4A since a pyramid like structure can improve the electronic connections between the individual LED structures and to the electrodes, and simplify the fabrication process as taught by Xu (paragraph 241). In regard to claim 17, Xu as described in Fig. 1B doesn’t explicitly teach a top dielectric layer continuously formed on a top surface of the micro LED array. Xu as described in Fig. 4A teaches a top dielectric layer (planarized layer 476) continuously formed on a top surface of the micro LED array (Fig. 4D and paragraph 335). It would’ve been obvious to one skilled in the art the time to combine the teachings of Xu as taught in Fig. 1B with Xu as taught in Fig. 4B to have a top dielectric layer continuously formed on a top surface of the micro LED array since this allows light to be emitted from the device while also protecting from unwanted shorts as taught by Xu (paragraph 335). In regard to claim 18, Xu as described in Figs. 1B and 4A teaches wherein the top dielectric layer is transparent (the planarized layer, such as 476, is transparent to the light emitted from the micro LED) (Fig. 4D and paragraph 335). In regard to claim 19, Xu as described in Figs. 1B and 4A teaches wherein material of the top dielectric layer is SiO2, SiN, SiON, or Al2O3 (the solid inorganic materials of the planarized layer 476 include SiO2) (paragraph 335). In regard to claim 20, Xu as described in Figs. 1B and 4A teaches a plurality of micro lenses (a micro-lens 602) provided on the top dielectric layer, each of the micro lenses covering a pixel display area of one of the micro LEDs (the single pixel tri-color LED device 600 has similar structures as any one of the single pixel tri-color LED devices shown in FIGS. 1-5 with the addition of a micro-lens 602) (Fig. 6A and paragraph 365). In regard to claim 21, Xu as described in Figs. 1B and 4A teaches wherein a diameter of a bottom surface of the micro lens is greater than a largest diameter of top surfaces of the two or more light emitting mesas (as shown in Fig. 6A the micro-lens 602 is shown with a bottom surface wider than a top surface than the LED light emitting layers 112, 130, and 136) (Fig. 6A). In regard to claim 22, Xu as described in Figs. 1B and 4A teaches wherein a height of the micro lens is equal to or less than 10 µm. (he height of the micro-lens 602 is not more than 2 micrometers) (paragraph 375). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Xu as applied to claim 9 above, in view of Xu et al. (US 2021/0305220 A1; hereinafter “Xu220”). In regard to claim 10, Xu doesn’t explicitly teach wherein the top conductive layer is continuously formed between adjacent micro LEDs. Xu220, teaches a micro LED array comprising a plurality of micro LEDs (a tri-color LED device 100) (Fig. 1A and paragraph 51), wherein a top conductive layer is continuously formed between adjacent micro LEDs (a transparent conductive layer 05 is shown continuously formed between the micro LED structures 01, 02 and 03 in Fig. 1A) (Fig. 1A and paragraphs 51 and 93). It would’ve been obvious to one skilled in the art to combine the teachings of Xu with the teachings of Xu220 to have the top conductive layer continuously formed between adjacent micro LEDs since this layout allows the manufacture of a device at reduced cost by reducing the intermediate steps and materials as taught by Xu (paragraph 95). Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Xu as applied to claim 1 above, in view of Wang et al. (CN114093905A; hereinafter “Wang”). In regard to claim 28, Xu doesn’t explicitly teach wherein a top most light emitting mesa emits green light. Wang teaches a micro LED array comprising a plurality of micro LEDs (a stacked Micro LED full-color display) (Fig. 1 and paragraph 47), wherein a top most light emitting mesa emits green light (the plurality of pixel light-emitting units are any combination of red light-emitting units, blue light emitting where unit 5 is a green light-emitting unit) (Fig. 3 and paragraph 49). It would’ve been obvious to one skilled in the art to combine the teachings of Xu with Wang to have a top most light emitting mesa emits green light since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893 /SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

May 02, 2024
Application Filed
Jun 04, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12684843
III-N SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME
4y 8m to grant Granted Jul 14, 2026
Patent 12628498
Display Substrate for Avoiding Lateral Leakage and Preparation Method Therefor, and Display Apparatus
4y 1m to grant Granted May 12, 2026
Patent 12622316
SEMICONDUCTOR STRUCTURE OF CELL ARRAY FORMED BY CELLS WITH HYBRID CELL HEIGHTS
4y 6m to grant Granted May 05, 2026
Patent 12613218
DEVICES AND METHODS FOR SELECTIVE DETECTION OF CANNABINOIDS
4y 5m to grant Granted Apr 28, 2026
Patent 12615952
METHOD FOR MANUFACTURING DISPLAY PANEL
2y 9m to grant Granted Apr 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
83%
With Interview (+6.1%)
3y 6m (~1y 3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 79 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month