DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 2 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of co-pending Application No. 18/623,082. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following:
18/654,027
18/623,082
Claim 1
An amplifier circuit having a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first node, a second node, a third node, a fourth node, a fifth node, and a sixth node, the amplifier circuit comprising:
An amplifier circuit having a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first node, a second node, a third node, a fourth node, a fifth node, a sixth node, a seventh node, an eighth node, a ninth node, and a tenth node, the amplifier circuit comprising: a first dynamic amplifier, comprising:
a first transistor having a first terminal, a second terminal, and a first control terminal, wherein the first terminal is coupled to the first node, the second terminal is coupled to the second output terminal, and the first control terminal is coupled to the first input terminal;
a first transistor having a first terminal, a second terminal, and a first control terminal, wherein the first terminal is coupled to the first node, the second terminal is coupled to the sixth node, and the first control terminal is coupled to the first input terminal;
a second transistor having a third terminal, a fourth terminal, and a second control terminal, wherein the third terminal is coupled to the second node, the fourth terminal is coupled to the second output terminal, and the second control terminal is coupled to the first input terminal;
a second transistor having a third terminal, a fourth terminal, and a second control terminal, wherein the third terminal is coupled to the second node, the fourth terminal is coupled to the sixth node, and the second control terminal is coupled to the first input terminal;
a third transistor having a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is coupled to the first node, the sixth terminal is coupled to the first output terminal, and the third control terminal is coupled to the second input terminal;
a third transistor having a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is coupled to the first node, the sixth terminal is coupled to the fifth node, and the third control terminal is coupled to the second input terminal;
a fourth transistor having a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is coupled to the second node, the eighth terminal is coupled to the first output terminal, and the fourth control terminal is coupled to the second input terminal;
a fourth transistor having a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is coupled to the second node, the eighth terminal is coupled to the fifth node, and the fourth control terminal is coupled to the second input terminal;
a first capacitor having a ninth terminal and a tenth terminal, wherein the ninth terminal is coupled to the third node and the tenth terminal is coupled to the fourth node;
a first capacitor having a ninth terminal and a tenth terminal, wherein the ninth terminal is coupled to the third node, and the tenth terminal is coupled to the fourth node;
a first switch coupled between the third node and a first reference voltage;
a first switch coupled between the third node and a first reference voltage;
a second switch coupled between the fourth node and a second reference voltage;
a second switch coupled between the fourth node and a second reference voltage;
a third switch coupled between the first node and the third node;
a third switch coupled between the first node and the third node; and
a fourth switch coupled between the second node and the fourth node;
a fourth switch coupled between the second node and the fourth node; and
a second capacitor having an eleventh terminal and a twelfth terminal, wherein the eleventh terminal is coupled to the fifth node, and the twelfth terminal is coupled to the sixth node;
a second dynamic amplifier, comprising:a fifth transistor having an eleventh terminal, a twelfth terminal, and a fifth control terminal, wherein the eleventh terminal is coupled to the seventh node, the twelfth terminal is coupled to the first output terminal, and the fifth control terminal is coupled to the sixth node;
a sixth transistor having a thirteenth terminal, a fourteenth terminal, and a sixth control terminal, wherein the thirteenth terminal is coupled to the eighth node, the fourteenth terminal is coupled to the first output terminal, and the sixth control terminal is coupled to the sixth node;
a seventh transistor having a fifteenth terminal, a sixteenth terminal, and a seventh control terminal, wherein the fifteenth terminal is coupled to the seventh node, the sixteenth terminal is coupled to the second output terminal, and the seventh control terminal is coupled to the fifth node;
an eighth transistor having a seventeenth terminal, an eighteenth terminal, and an eighth control terminal, wherein the seventeenth terminal is coupled to the eighth node, the eighteenth terminal is coupled to the second output terminal, and the eighth control terminal is coupled to the fifth node;
a fifth switch coupled between the fifth node and a third reference voltage;
a sixth switch coupled between the sixth node and a fourth reference voltage;
a seventh switch coupled between the first node and the fifth node; and
an eighth switch coupled between the second node and the sixth node.
a second capacitor having a nineteenth terminal and a twentieth terminal, wherein the nineteenth terminal is coupled to the ninth node, and the twentieth terminal is coupled to the tenth node;
a fifth switch coupled between the ninth node and a third reference voltage;
a sixth switch coupled between the tenth node and a fourth reference voltage;
a seventh switch coupled between the seventh node and the ninth node; and
an eighth switch coupled between the eighth node and the tenth node.
Claim 2 of the present application is identical to Claim 2 of the co-pending application. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 and 5 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Zhao (High-performance swing-enhanced floating inverter amplifier using correlated level shifting technique).
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Figure I: Fig. 4(a) of Zhao as annotated by examiner
Regarding claim 1, Zhao discloses, per Figure I, an amplifier circuit having a first input terminal (left VCM), a second input terminal (right VCM), a first output terminal (VON), a second output terminal (VOP), a first node (N1), a second node (N2), a third node (N3), a fourth node (N4), a fifth node (N5), and a sixth node (N6), the amplifier circuit comprising:
a first transistor (PMOS 1) having a first terminal (PMOS 1 source), a second terminal (PMOS 1 drain), and a first control terminal (PMOS1 gate), wherein the first terminal (PMOS 1 source) is coupled to the first node (N1), the second terminal (PMOS 1 drain) is coupled to the second output terminal (VON), and the first control terminal (PMOS 1 gate) is coupled to the first input terminal (left VCM);
a second transistor (NMOS 1) having a third terminal, a fourth terminal, and a second control terminal (NMOS 1 gate), wherein the third terminal (NMOS 1 source) is coupled to the second node (N2), the fourth terminal (NMOS 1 drain) is coupled to the second output terminal (VON), and the second control terminal (NMOS 1 gate) is coupled to the first input terminal (left VCM);
a third transistor (PMOS 2) having a fifth terminal (PMOS 2 source), a sixth terminal (PMOS 2 drain), and a third control terminal (PMOS 2 gate), wherein the fifth terminal (PMOS 2 source) is coupled to the first node (N1), the sixth terminal (PMOS 2 drain) is coupled to the first output terminal (VOP), and the third control terminal (PMOS 2 gate) is coupled to the second input terminal (right VCM);
a fourth transistor (NMOS 2) having a seventh terminal (NMOS 2 source), an eighth terminal (NMOS 2 drain), and a fourth control terminal (NMOS 2 gate), wherein the seventh terminal (NMOS 2 source) is coupled to the second node (N2), the eighth terminal (NMOS 2 drain) is coupled to the first output terminal (VOP), and the fourth control terminal (NMOS 2 gate) is coupled to the second input terminal (right VCM);
a first capacitor (CRES1) having a ninth terminal and a tenth terminal, wherein the ninth terminal (top terminal of CRES1) is coupled to the third node (N3) and the tenth terminal (bottom terminal of CRES1) is coupled to the fourth node (N4);
a first switch (SWp1 on position) coupled between the third node (N3) and a first reference voltage (VH1);
a second switch (SWn1 on position) coupled between the fourth node (N4) and a second reference voltage (VL1);
a third switch (SWp2 on position) coupled between the first node (N1) and the third node (N3);
a fourth switch (SWn2 on position) coupled between the second node (N2) and the fourth node (N4);
a second capacitor (CRES2) having an eleventh terminal (top terminal of CRES2) and a twelfth terminal (bottom terminal of CRES2), wherein the eleventh terminal (top terminal of CRES2) is coupled to the fifth node (N5), and the twelfth terminal (bottom terminal of CRES2) is coupled to the sixth node (N6);
a fifth switch (SWp3 on position) coupled between the fifth node (N5) and a third reference voltage (VH2);
a sixth switch (SWn3 on position) coupled between the sixth node (N6) and a fourth reference voltage (VL2);
a seventh switch (SWp4 on position) coupled between the first node (N1) and the fifth node (N5); and
an eighth switch (SWn4 on position) coupled between the second node (N2) and the sixth node (N6).
Regarding Claim 5, Zhao discloses that a capacitance value of the first capacitor (CRES1) is not equal to a capacitance value of the second capacitor (CRES2), by stating that “…the SEFIA is supplied by the capacitor CRES2 which is bigger than the CRES1” (page 3, paragraph 2, line 3).
Allowable Subject Matter
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art references do not teach that a duration during which the first clock is at the second level is not equal to a duration during which the second clock is at the second level.
Regarding claim 4, the prior art references do not teach that a difference between the first reference voltage and the second reference voltage is not equal to a difference between the third reference voltage and the fourth reference voltage.
Claims 6-10 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claims 6-10 are allowed over the prior art of record, Sun (U.S. 2021/0384874). The prior art of record considered individually or in combination, fails to fairly teach or suggest the claimed amplifier circuit comprising, among other limitations and unobvious limitations of:
Regarding claim 6, Sun (US 2021/0384874 A1) teaches an amplifier circuit having a first input terminal (VI+), a second input terminal (VI-), a first output terminal (Vx+), a second output terminal (Vx), a first node, a second node, a third node, and a fourth node, the amplifier circuit comprising:
a first transistor (M1) having a first terminal (M1 source), a second terminal (M1 drain), and a first control terminal (M1 gate), wherein the first terminal is coupled to the first node (1), the second terminal (M1 drain) is coupled to the second output terminal (Vx-), and the first control terminal (M1 gate) is coupled to the first input terminal (VI+);
a second transistor (M3) having a third terminal (M3 source), a fourth terminal (M3 drain), and a second control terminal (M3 gate), wherein the third terminal (M3 source) is coupled to the second node (2), the fourth terminal (M3 drain) is coupled to the second output terminal (Vx-), and the second control terminal (M3 gate) is coupled to the first input terminal (VI+);
a third transistor (M2) having a fifth terminal (M2 source), a sixth terminal (M2 drain), and a third control terminal (M2 gate), wherein the fifth terminal (M2 source) is coupled to the first node (1), the sixth terminal (M2 drain) is coupled to the first output terminal (Vx+), and the third control terminal (M2 gate) is coupled to the second input terminal (VI-);
a fourth transistor (M4) having a seventh terminal (M4 source), an eighth terminal (M4 drain), and a fourth control terminal (M4 gate), wherein the seventh terminal (M4 source) is coupled to the second node (2), the eighth terminal (M4 drain) is coupled to the first output terminal (Vx+), and the fourth control terminal (M4 gate) is coupled to the second input terminal (VI-);
a capacitor (Cres) having a ninth terminal (9) and a tenth terminal (10), wherein the ninth terminal (9) is coupled to the third node (3), and the tenth terminal (10) is coupled to the fourth node (4);
a capacitor (Cres) having a ninth terminal (9) and a tenth terminal (10), wherein the ninth terminal (9) is coupled to the third node (3), and the tenth terminal (10) is coupled to the fourth node (4);
a first switch (S1) coupled between the third node (3) and a first reference voltage (ground);
a first switch (S1) coupled between the third node (3) and a first reference voltage (ground);
a second switch (S2) coupled between the fourth node (4) and a second reference voltage (Vdd);
a third switch (S3) coupled between the first node (1) and the third node (3);
a fourth switch (S4) coupled between the second node (2) and the fourth node (4);
However, the above reference, when taken alone or in combination does not fairly teach
nor render obvious the limitation “a fifth switch coupled between the third node and a third reference voltage; and a sixth switch coupled between the fourth node and a fourth reference voltage.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AHMED RAYEED whose telephone number is (571)270-7528. The examiner can normally be reached 7:30 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AHMED RAYEED/Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
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