Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner notes the instant application states: [0019] A computer readable storage medium, as that term is used in the present disclosure, is not to be construed as storage in the form of transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses passing through a fiber optic cable, electrical signals communicated through a wire, and/or other transmission media.
For this reason, Examiner has interpreted claims 15 and associated dependent claims as having structure.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Regarding independent claims the limitations of determining steps, allocating steps (i.e. assigning), as drafted, recites functions that, under its broadest reasonable interpretation, covers a function that could reasonably be performed in the mind, including with the aid of pen and paper, but for the recitation of generic computer components. That is, the limitations as cited above as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process.
Thus, these limitation falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, this judicial exception is not integrated into a practical application. The claim recites the following additional limitations: memory, processor, processing devices, storage media, processor chips. The additional elements are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computer, and/or mere computer components, MPEP 2106.05(f), and steps of receiving do nothing more than add insignificant extra solution activity to the judicial exception of merely gathering data. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g) (Ex. v. Consulting and updating an activity log, Ultramercial, 772 F.3d at 715, 112 USPQ2d at 1754).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements memory, processor, processing devices, storage media, processor chips, amount to no more than mere instructions, or generic computer/computer components to carry out the exception. Furthermore, the limitations directed to receiving the courts have identified mere data gathering is well-understood, routine and conventional activity. See MPEP 2106.05(d) (Ex. iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93;).
The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101.
Regarding claims 2, 3, 4, 6, 9, 10, 11, 13, 16, 17, 18, 20 the limitations of beginning allocation, selecting, allocating, generating, determining, identifying, marking, deducting, are functions that can be reasonably performed in the human mind, thus, additional mental process defined in the claims. The claim does not include any additional element, thus, no limitation that needs to be analyzed under prong 2 for practical application, or under step 2B for significantly more.
Regarding claim 5, 7, 12, 14, 19 the limitation of what drawers/chips/processors comprise are considered mere instructions, or generic computer/computer components to carry out the exception Accordingly, the additional element recited in claim 3 fails to provide a practical application under prong 2, or amount to significantly more under step 2B.
Claim Rejections - 35 USC §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim/s 1, 5, 8, 12, 15, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Havlir (Pub. No. US 2023/0050061) in view of Brady (Pat. No. US 12,182,926).
Claim 1, 8, 15, Havlir teaches “a computer-implemented method comprising: receiving a request to create a logical partition for a computing environment ([0381] memory, processors [0055] Kickslot manager 350, in the illustrated embodiment, is configured to receive kicks from the software/firmware interface and communicate kicks to primary control circuitry 210 for assignment to logical slots.), the computing environment comprising a plurality of drawers ([Fig. 4] ex. group 0 as a drawer), each of the plurality of drawers comprising a plurality of nodes ([Fig. 4] ex. mGPU0 as a node), each of the plurality of nodes comprising a plurality of processor chips ([Fig. 4] ex. DS0 as a chip), each of the plurality of processor chips having a plurality of processor cores being of one of a plurality of processor core types (Examiner notes, as evidence by Brady, the mGPU comprises different circuitry types with cores, for example shader cores and therefore would be obvious to one of ordinarily skilled in the art, Hablir comprises chips of cores of a type for the purposes of design choice [Col. 6, Lines 19-35] (33) FIG. 2 is a block diagram illustrating example geometry work distribution to circuitry of a graphics processor, according to some embodiments. In the illustrated embodiment, the processor includes primary vertex control circuitry 210, distributed vertex control circuits 220A-220N, geometry processing pipelines 230A-230N, and shader circuitry 240A-240N. In some embodiments, each distributed vertex control circuit is implemented in a different processor sub-unit, e.g., an mGPU. Each mGPU may be configured to execute programs in parallel and may include: fragment generator circuitry, shader core circuitry configured to execute shader programs, memory system circuitry (which may include one or more caches and a memory management unit), geometry processing circuitry, and distributed workload distribution circuitry (such as distributed vertex control 220) which may coordinate with primary control circuitry to distribute work to shader pipelines. [Col. 13, Lines 60-63] Graphics unit 875, in various embodiments, may include programmable shader circuitry which may include highly parallel execution cores); determining whether the logical partition can be implemented on a single drawer of the plurality of drawers; responsive to determining that the logical partition can be implemented on a single drawer of the plurality of drawers, allocating the logical partition to one of the drawers of the plurality of drawers based on a container size that can fit the logical partition ([0059] Mode A, in the illustrated example, is a single-mGPU distribution mode. In this mode, control circuitry 215 assigns work from the logical slot to a single hardware slot on a single mGPU. [Fig. 4] example A ); and responsive to determining that the logical partition cannot be implemented on a single drawer of the plurality of drawers, allocating the logical partition to at least two drawers of the plurality of drawers using bitmasks ([0061] Mode C, in the illustrated example, is a larger multi-group distribution mode. In this mode, control circuitry 215 assigns work from the logical slot to a slot in each mGPU of multiple groups of mGPUs (e.g., every group on the graphics processor, in some embodiments).), wherein each of the bitmasks represents a processor chip of the plurality of processor chips, and wherein one bitmask is generated per drawer of the plurality of drawers ([0091] FIG. 9 is a diagram illustrating example software override fields. Software or firmware may adjust these fields to control kernel distribution. The mGPU mask field, in the illustrated embodiment, indicates which mGPUs can be used by this kick. For example, the mask may include a bit per mGPU. This may allow software to indicate that avoid or target certain mGPUs for the kick. The distribution mode field allows software to select a distribution mode. The default value may allow the control stream processor 630 for the logical slot to select a distribution mode. The other values may specify a distribution mode, which may be implemented by a control stream processor 630 regardless of the mode it would have chosen (at least in operating modes in which software overrides are enabled). In the default mode, the mGPU assign circuitry 650 may select dSlots according to the distribution mode selected by a CSP flexibly, based on load balancing, while in other modes the mGPU assign circuitry may follow restrictions specified by software overrides. [0092] The force group field allows software to select a group on which to execute a kick. This may be specified in conjunction with single mGPU or single group distribution modes, for example. The policy field allows software to specify a scheduling policy for single mGPU or single group distribution. In the illustrated example, software can specify a “select first option” policy (which may be the default) or a round robin policy. The select first option policy may select the first available element (e.g., mGPU or group) according to their index, which may avoid fragmentation and leave more contiguous dSlots free for other slices. The round robin policy may randomize usage of resources which may avoid the location of selected resources causing substantial performance variation but may spread small slices over multiple groups. In other embodiments, various policies may be specified. Detailed examples of arbitration that considers software override fields are discussed below.)”.
Claim 5, 12, 19, the combination teaches the claim, wherein Havlir teaches “the computer-implemented method of claim 1, wherein the plurality of drawers is four drawers ([Fig. 5] four groups), wherein the plurality of nodes is four nodes ([Fig. 5] four mGPU per group), and wherein the plurality of processor chips is two processor chips ([0192] Reciting that “a set of graphics processor sub-units each implement multiple distributed hardware slots” means that the set of graphics processor sub-units includes at least two sub-units, each of which implements multiple distributed hardware slots.)”.
Claim/s 6, 7, 13, 14, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Havlir, Brady in further view of KI (Pub. No. US 2019/0146837).
Claim 6, 13, 20, the combination may not explicitly teach the limitation.
KI teaches “the computer-implemented method of claim 1, wherein allocating the logical partition to one of the drawers of the plurality of drawers is further responsive to the partition only certain types of processors ([0180] In yet another embodiment, the mapping processor 1182 may analyze the task 172 and determine if it includes a specific or one of a specific number of operations. If so, the mapping processor 1182 may be configured to assign the task 172 to an associated processor or type of processor (e.g., CPU, GPU, general purpose GPU (GPGPU)). In various embodiments, the mapping processor 1182 may include a preconfigured list of operation sequences and their associated processors. In another embodiment, the mapping processor 1182 may dynamically build the list of sequences over time, or remember what assignment the sequence last received. It is understood that the above are merely a few illustrative examples to which the disclosed subject matter is not limited.)”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of KI with the teachings of Havlir, Brady in order to provide a system that teaches partitioning resources. The motivation for applying KI teaching with Havlir, Brady teaching is to provide a system that allows for configuration design choice. Havlir, Brad, KI are analogous art directed towards system configuration. Together Havlir, Brad, KI teach every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of KI with the teachings of Havlir, Brad by known methods and gained expected results.
Claim 7, 14 the combination teaches the claim, wherein KI teaches “the computer-implemented method of claim 6, wherein the certain types of processors comprise a general-purpose processor and an integrated information processor ([0180] In yet another embodiment, the mapping processor 1182 may analyze the task 172 and determine if it includes a specific or one of a specific number of operations. If so, the mapping processor 1182 may be configured to assign the task 172 to an associated processor or type of processor (e.g., CPU, GPU, general purpose GPU (GPGPU)). In various embodiments, the mapping processor 1182 may include a preconfigured list of operation sequences and their associated processors. In another embodiment, the mapping processor 1182 may dynamically build the list of sequences over time, or remember what assignment the sequence last received. It is understood that the above are merely a few illustrative examples to which the disclosed subject matter is not limited.)”.
Rationale to claim 6 is applied here.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WYNUEL S AQUINO whose telephone number is (571)272-7478. The examiner can normally be reached 9AM-5PM EST M-F.
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/WYNUEL S AQUINO/Primary Examiner, Art Unit 2199
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