DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' application filed on 05/03/24. Claims 1-10 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8-10 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhong et al. (US 20140340067 A1)
[Claim 1] Zhong teaches a power control device [controller of fig2] configured to serve as a main controlling agent in a power supply device [LDO of fig 2] which generates an output voltage [vout] from an input voltage [VDD] using an output transistor [220], the power control device comprising:
an output feedback circuit [see 11] configured to receive the output voltage or a feedback voltage [i.e. Vfb] corresponding to the output voltage to generate a driving signal [output of 211] for the output transistor;
a current feedback signal generation circuit [circuit between 209 and 217 w/ voltage divider of 204] configured to generate a current feedback signal [Vfb] for adjusting phase characteristics [i.e. controlling output of 211] of the output feedback circuit according to an output current [a change in Ipass inherently produces a change in Iload as equations in ¶50 and ¶52 show Iload is express similar to Ipass] of the power supply device;
and a delay circuit [206] configured to delay a change [inherent function of RC circuit] in the current feedback signal in response to a change in the output current [output of 211 is indirectly driven by the Vfb].
[Claim 8] Zhong teaches the power control device according to claim 1, wherein the output feedback circuit includes an error amplifier [211] configured to generate an error signal corresponding to a difference between the output voltage or the feedback voltage and a predetermined reference voltage [201].
[Claim 9] Zhong teaches the power control device according to claim 8, wherein the output feedback circuit controls characteristics of the error amplifier according to the current feedback signal [i.e. Vfb].
[Claim 10] Zhong teaches a power supply device comprising the power control device [power control device of fig 2] according to claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 5 rejected under 35 U.S.C. 103 as being unpatentable over Zhong et al. (US 20140340067 A1) in view of Cho et al. (US 20080088286 A1)
[Claim 2] Zhong teaches the power control device according to claim 1, However, Zhong does not explicitly mention wherein the current feedback signal generation circuit includes: a mirror transistor configured to be driven according to the driving signal so as to generate a mirror current corresponding to the output current; and a current mirror configured to generate the current feedback signal from the mirror current.
Cho teaches a circuit wherein the current feedback signal generation circuit [circuit between opamp and Mp1 of fig 6] includes: a mirror transistor [see 610] configured to be driven according to the driving signal so as to generate a mirror current corresponding to the output current [¶28]; and a current mirror [606/610] configured to generate the current feedback signal from the mirror current [¶28].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Cho in order to provide isolation between the gate and opamp while allowing opamp to stay in linear region, thus, allowing for better phase margin.
[Claim 5] Zhong as modified teaches the power control device according to claim 2, wherein the delay circuit delays a change in the current feedback signal output from the current mirror in response to a change in the mirror current input to the current mirror [implicit from equation of ¶50 Zhong].
Allowable Subject Matter
Claims 3, 4, 6, 7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838